MT46H32M16LGBF-5:C datasheet, PDF

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MT46H32M16LGBF-5:C: DescriptionDDR DRAM, 32MX16, CMOS, PBGA60, 9 X 8 MM, GREEN, PLASTIC, VFBGA-60; Categorystorage storage; File Size3MB，95 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT46H32M16LGBF-5:C Overview

DDR DRAM, 32MX16, CMOS, PBGA60, 9 X 8 MM, GREEN, PLASTIC, VFBGA-60

MT46H32M16LGBF-5:C Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	BGA
package instruction	VFBGA,
Contacts	60
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B60
JESD-609 code	e1
length	9 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	60
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX16
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm

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Micron Confidential and Proprietary

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‡

512Mb: x16, x32 Mobile LPDDR SDRAM

Features

Mobile Low-Power DDR SDRAM

MT46H32M16LF – 8 Meg x 16 x 4 Banks

MT46H16M32LF – 4 Meg x 32 x 4 Banks

MT46H16M32LG – 4 Meg x 32 x 4 Banks

Features

•

DDQ

= 1.70–1.95V

•

Bidirectional data strobe per byte of data (DQS)

•

Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

•

Differential clock inputs (CK and CK#)

•

Commands entered on each positive CK edge

•

DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

•

4 internal banks for concurrent operation

•

Data masks (DM) for masking write data; one mask

per byte

•

Programmable burst lengths (BL): 2, 4, 8, or 16

•

Concurrent auto precharge option is supported

•

Auto refresh and self refresh modes

•

1.8V LVCMOS-compatible inputs

•

Temperature-compensated self refresh (TCSR)

•

Partial-array self refresh (PASR)

•

Deep power-down (DPD)

•

Status read register (SRR)

•

Selectable output drive strength (DS)

•

Clock stop capability

•

64ms refresh

Table 1: Key Timing Parameters (CL = 3)

Speed Grade

-5

-54

-6

-75

Clock Rate

200 MHz

185 MHz

166 MHz

133 MHz

Access Time

5.0ns

6.0ns

Options

•

DDQ

–

1.8V/1.8V

•

Configuration

–

32 Meg x 16 (8 Meg x 16 x 4 banks)

–

16 Meg x 32 (4 Meg x 32 x 4 banks)

•

Addressing

–

JEDEC-standard addressing

–

Reduced page size

•

Plastic "green" package

–

60-ball VFBGA (8mm x 9mm)

–

90-ball VFBGA (8mm x 13mm)

•

Timing – cycle time

–

5ns @ CL = 3 (200 MHz)

–

5.4ns @ CL = 3 (185 MHz)

–

6ns @ CL = 3 (166 MHz)

–

7.5ns @ CL = 3 (133 MHz)

•

Power

–

Standard I

DD2

DD6

–

Low-power I

DD2

DD6

•

Operating temperature range

–

Commercial (0˚ to +70˚C)

–

Industrial (–40˚C to +85˚C)

–

Automotive (–40˚C to +105˚C)

•

Design revision

Notes:

Marking

32M16

16M32

-5

-54

-6

-75

None

1. Only available for x16 configuration.

2. Only available for x32 configuration.

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Micron Confidential and Proprietary

Advance

512Mb: x16, x32 Mobile LPDDR SDRAM

General Description ......................................................................................................................................... 7

Functional Block Diagrams ............................................................................................................................... 8

Ball Assignments ............................................................................................................................................ 10

Ball Descriptions ............................................................................................................................................ 12

Package Dimensions ...................................................................................................................................... 14

Electrical Specifications .................................................................................................................................. 16

Electrical Specifications – I

Parameters ........................................................................................................ 19

Electrical Specifications – AC Operating Conditions ......................................................................................... 25

Output Drive Characteristics ........................................................................................................................... 30

Functional Description ................................................................................................................................... 33

Commands .................................................................................................................................................... 34

DESELECT ................................................................................................................................................ 35

NO OPERATION ........................................................................................................................................ 35

LOAD MODE REGISTER ............................................................................................................................ 35

ACTIVE ..................................................................................................................................................... 35

READ ........................................................................................................................................................ 36

WRITE ...................................................................................................................................................... 37

PRECHARGE ............................................................................................................................................. 38

BURST TERMINATE .................................................................................................................................. 39

AUTO REFRESH ........................................................................................................................................ 39

SELF REFRESH ........................................................................................................................................... 40

DEEP POWER-DOWN ................................................................................................................................ 40

Truth Tables ................................................................................................................................................... 41

State Diagram ................................................................................................................................................ 46

Initialization .................................................................................................................................................. 47

Standard Mode Register .................................................................................................................................. 50

Burst Length .............................................................................................................................................. 50

Burst Type ................................................................................................................................................. 51

CAS Latency .............................................................................................................................................. 52

Operating Mode ......................................................................................................................................... 53

Extended Mode Register ................................................................................................................................. 54

Temperature-Compensated Self Refresh .................................................................................................... 54

Partial-Array Self Refresh ........................................................................................................................... 55

Output Drive Strength ................................................................................................................................ 55

Status Read Register ....................................................................................................................................... 56

Bank/Row Activation ...................................................................................................................................... 58

READ Operation ............................................................................................................................................. 59

WRITE Operation ........................................................................................................................................... 70

PRECHARGE Operation .................................................................................................................................. 82

Auto Precharge ............................................................................................................................................... 82

Concurrent Auto Precharge ........................................................................................................................ 83

AUTO REFRESH Operation ............................................................................................................................. 88

SELF REFRESH Operation .............................................................................................................................. 89

Power-Down .................................................................................................................................................. 90

Deep Power-Down .................................................................................................................................... 92

Clock Change Frequency ................................................................................................................................ 94

Revision History ............................................................................................................................................. 95

Rev. B – 02/10 ............................................................................................................................................. 95

Rev. A – 01/10 ............................................................................................................................................. 95

Contents

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Micron Confidential and Proprietary

Advance

512Mb: x16, x32 Mobile LPDDR SDRAM

Table 1: Key Timing Parameters (CL = 3) .......................................................................................................... 1

Table 2: Configuration Addressing .................................................................................................................. 2

Table 3: Ball Descriptions .............................................................................................................................. 12

Table 4: Absolute Maximum Ratings .............................................................................................................. 16

Table 5: AC/DC Electrical Characteristics and Operating Conditions ............................................................... 16

Table 6: Capacitance (x16, x32) ...................................................................................................................... 18

Table 7: I

Specifications and Conditions, –40°C to +85°C (x16) ..................................................................... 19

Table 8: I

Specifications and Conditions, –40°C to +85°C (x32) ..................................................................... 20

Table 9: I

Specifications and Conditions, –40°C to +105°C (x16) ................................................................... 21

Table 10: I

Specifications and Conditions, –40°C to +105°C (x32) ................................................................. 22

Table 11: I

DD6

Specifications and Conditions .................................................................................................. 23

Table 12: Electrical Characteristics and Recommended AC Operating Conditions ............................................ 25

Table 13: Target Output Drive Characteristics (Full Strength) .......................................................................... 30

Table 14: Target Output Drive Characteristics (Three-Quarter Strength) .......................................................... 31

Table 15: Target Output Drive Characteristics (One-Half Strength) ................................................................. 32

Table 16: Truth Table – Commands ............................................................................................................... 34

Table 17: DM Operation Truth Table ............................................................................................................. 35

Table 18: Truth Table – Current State Bank

– Command to Bank

............................................................... 41

Table 19: Truth Table – Current State Bank

– Command to Bank

.............................................................. 42

Table 20: Truth Table – CKE .......................................................................................................................... 45

Table 21: Burst Definition Table .................................................................................................................... 51

List of Tables

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Micron Confidential and Proprietary

Advance

512Mb: x16, x32 Mobile LPDDR SDRAM

Figure 1: 512Mb Mobile LPDDR Part Numbering ............................................................................................. 2

Figure 2: Functional Block Diagram (x16) ......................................................................................................... 8

Figure 3: Functional Block Diagram (x32) ......................................................................................................... 9

Figure 4: 60-Ball VFBGA – Top View, x16 only ................................................................................................. 10

Figure 5: 90-Ball VFBGA – Top View, x32 only ................................................................................................. 11

Figure 6: 60-Ball VFBGA (8mm x 9mm), Package Code: BF .............................................................................. 14

Figure 7: 90-Ball VFBGA (8mm x 13mm), Package Code: B5 ............................................................................ 15

Figure 8: Typical Self Refresh Current vs. Temperature – TBD ......................................................................... 24

Figure 9: ACTIVE Command .......................................................................................................................... 36

Figure 10: READ Command ........................................................................................................................... 37

Figure 11: WRITE Command ......................................................................................................................... 38

Figure 12: PRECHARGE Command ................................................................................................................ 39

Figure 13: DEEP POWER-DOWN Command .................................................................................................. 40

Figure 14: Simplified State Diagram ............................................................................................................... 46

Figure 15: Initialize and Load Mode Registers ................................................................................................. 48

Figure 16: Alternate Initialization with CKE LOW ............................................................................................ 49

Figure 17: Standard Mode Register Definition ................................................................................................ 50

Figure 18: CAS Latency .................................................................................................................................. 53

Figure 19: Extended Mode Register ................................................................................................................ 54

Figure 20: Status Read Register Timing .......................................................................................................... 56

Figure 21: Status Register Definition .............................................................................................................. 57

Figure 22: READ Burst ................................................................................................................................... 60

Figure 23: Consecutive READ Bursts .............................................................................................................. 61

Figure 24: Nonconsecutive READ Bursts ........................................................................................................ 62

Figure 25: Random Read Accesses ................................................................................................................. 63

Figure 26: Terminating a READ Burst ............................................................................................................. 64

Figure 27: READ-to-WRITE ............................................................................................................................ 65

Figure 28: READ-to-PRECHARGE .................................................................................................................. 66

Figure 29: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x16) ................................................... 67

Figure 30: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x32) ................................................... 68

Figure 31: Data Output Timing –

AC and

DQSCK .......................................................................................... 69

Figure 32: Data Input Timing ......................................................................................................................... 71

Figure 33: Write – DM Operation ................................................................................................................... 72

Figure 34: WRITE Burst ................................................................................................................................. 73

Figure 35: Consecutive WRITE-to-WRITE ....................................................................................................... 74

Figure 36: Nonconsecutive WRITE-to-WRITE ................................................................................................. 74

Figure 37: Random WRITE Cycles .................................................................................................................. 75

Figure 38: WRITE-to-READ – Uninterrupting ................................................................................................. 76

Figure 39: WRITE-to-READ – Interrupting ...................................................................................................... 77

Figure 40: WRITE-to-READ – Odd Number of Data, Interrupting .................................................................... 78

Figure 41: WRITE-to-PRECHARGE – Uninterrupting ...................................................................................... 79

Figure 42: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 80

Figure 43: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting ......................................................... 81

Figure 44: Bank Read – With Auto Precharge .................................................................................................. 84

Figure 45: Bank Read – Without Auto Precharge ............................................................................................. 85

Figure 46: Bank Write – With Auto Precharge .................................................................................................. 86

Figure 47: Bank Write – Without Auto Precharge ............................................................................................. 87

Figure 48: Auto Refresh Mode ........................................................................................................................ 88

Figure 49: Self Refresh Mode ......................................................................................................................... 90

Figure 50: Power-Down Entry (in Active or Precharge Mode) .......................................................................... 91

List of Figures

PDF: 09005aef83dd2b3e

t67m_512mb_mobile_lpddr.pdf - Rev. B 2/10 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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