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GS71116J-10T

Description
Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
Categorystorage    storage   
File Size220KB,15 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Download Datasheet Parametric View All

GS71116J-10T Overview

Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, SOJ-44

GS71116J-10T Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerGSI Technology
Parts packaging codeSOJ
package instructionSOJ,
Contacts44
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time10 ns
JESD-30 codeR-PDSO-J44
length28.58 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals44
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX16
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height3.76 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
GS71116TP/J/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 10, 12, 15ns
• CMOS low power operation: 100/85/70 mA at min. cycle time.
• Single 3.3V ± 0.3V power supply
• All inputs and outputs are TTL compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: -40° to 85°C
• Package line up
J: 400mil, 44 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
64K x 16
1Mb Asynchronous SRAM
SOJ 64K x 16 Pin Configuration
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
DQ
3
DQ
4
V
DD
V
SS
DQ
5
DQ6
DQ7
DQ
8
WE
A
15
A
14
A
13
A
12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10, 12, 15ns
3.3V V
DD
Center V
DD
& V
SS
Top view
44 pin
SOJ
Description
The GS71116 is a high speed CMOS static RAM organized as
65,536-words by 16-bits. Static design eliminates the need for exter-
nal clocks or timing strobes. Operating on a single 3.3V power supply
and all inputs and outputs are TTL compatible. The GS71116 is avail-
able in a 6x8 mm Fine Pitch BGA package as well as in 400 mil SOJ
and 400 mil TSOP Type-II packages.
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
5
A
6
A
7
OE
UB
LB
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
V
DD
DQ
12
DQ
11
DQ
10
DQ
9
NC
A
8
A
9
A
10
A
11
NC
Pin Descriptions
Symbol
A
0
to A
15
DQ
1
to DQ
16
CE
LB
UB
WE
OE
V
DD
V
SS
NC
Description
Address input
Data input/output
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3V power supply
Ground
No connect
Fine Pitch BGA 64K x 16 Bump Configuration
1
2
3
4
5
6
A
B
C
D
E
F
G
H
LB
DQ
16
OE
UB
A
0
A
3
A
5
NC
NC
A
8
A
10
A
13
A
1
A
4
A
6
A
7
NC
A
9
A
11
A
14
A
2
CE
DQ
2
DQ
4
DQ
5
DQ
7
WE
A
15
NC
DQ
1
DQ
3
V
DD
V
SS
DQ
6
DQ
8
NC
DQ
14
DQ
15
V
SS
V
DD
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
NC
NC
A
12
6mm x 8mm, 0.75mm Bump Pitch
Top View
Rev: 1.06 6/2000
1/15
© 1999, Giga Semiconductor, Inc.
M
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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