L10C11PC15 datasheet, PDF - EEWORLD Datasheet

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L10C11PC15: DescriptionPipeline Register, 8-Bit, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24; CategoryThe embedded processor and controller Microcontrollers and processors; File Size76KB，6 Pages; ManufacturerLOGIC Devices; Websitehttp://www.logicdevices.com/

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L10C11PC15 Overview

Pipeline Register, 8-Bit, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24

L10C11PC15 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	LOGIC Devices
Parts packaging code	DIP
package instruction	DIP,
Contacts	24
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Other features	SELECTABLE DELAY LENGTH FROM 3 TO 18 STAGES; ICC SPECIFIED AT 5MHZ
boundary scan	NO
maximum clock frequency	66.66 MHz
External data bus width	8
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
length	30.861 mm
low power mode	NO
Humidity sensitivity level	3
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
Output data bus width	8
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum slew rate	20 mA
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, PIPELINE REGISTER

L10C11PC15 Preview

L10C11

DEVICES INCORPORATED

4/8-bit Variable Length Shift Register

L10C11

DEVICES INCORPORATED

4/8-bit Variable Length Shift Register

DESCRIPTION

The

L10C11

is a high-speed, low

power CMOS variable length shift

register. The L10C11 consists of two

4-bit wide, adjustable length shift

registers. These registers share control

signals and a common clock. Both

shift registers can be programmed

together to any length from 3 to 18

stages inclusive, or one register can be

fixed at 18 stages of delay while the

other is variable. The configuration

implemented is determined by the

Length Code (L

3-0

) and the MODE

control line as shown in Table 1.

Each input is applied to a chain of

registers which are clocked on the

rising edge of the common CLK input.

These registers are numbered R1

through R17 and R1’ through R17’,

corresponding to the D

3-0

and D

7-4

data fields respectively. A multi-

plexer serves to route the contents of

any of registers R2 through R17 to the

output register, denoted R18. A

similar multiplexer operates on the

contents of R2’ through R17’ to load

R18’. Note that the minimum-length

path from data inputs to outputs is R1

to R2 to R18, consisting of three stages

of delay.

The MODE input determines whether

one or both of the internal shift

registers have variable length. When

MODE = 0, both D

3-0

and D

7-4

are

delayed by an amount which is

controlled by L

3-0

. When MODE = 1,

the D

7-4

field is delayed by 18 stages

independent of L

3-0

.

The Length Code (L

3-0

) controls the

number of stages of delay applied to

the D inputs as shown in Table 1.

When the Length Code is 0, the inputs

are delayed by 3 clock periods. When

the Length Code is 1, the delay is 4

clock periods, and so forth. The

Length Code and MODE inputs are

latched on the rising edge of CLK.

Both the Length Code and MODE

values may be changed at any time

without affecting the contents of

registers R1 through R17 or R1’

through R17’.

FEATURES

u

Variable Length 4 or 8-bit Wide

Shift Register

u

Selectable Delay Length from 3 to

18 Stages

u

Low Power CMOS Technology

Replaces Fairchild TMC2011

Load, Shift, and Hold Instructions

Separate Data In and Data Out Pins

Package Styles Available:

• 24-pin Plastic DIP

• 28-pin Plastic LCC, J-Lead

L10C11 B

LOCK

D

IAGRAM

REGISTER R15

REGISTER R16

REGISTER R17

REGISTER R18

REGISTER R1

REGISTER R2

REGISTER R3

R17

R16

R15

MUX

4

D

3-0

4

Y

3-0

CLK

4

L

3-0

R4

R3

R2

MODE

L REGISTER

REGISTER R15’

REGISTER R16’

REGISTER R17’

REGISTER R18’

REGISTER R1’

REGISTER R2’

REGISTER R3’

R17’

R16’

R15’

MUX

4

D

7-4

4

Y

7-4

R4’

R3’

R2’

Pipeline Registers

1

03/27/2000–LDS.11-L

L10C11

DEVICES INCORPORATED

4/8-bit Variable Length Shift Register

M

AXIMUM

R

ATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

Storage temperature ..................................................... –65°C to +150°C

Operating ambient temperature ..................................... –55°C to +125°C

V

CC

supply voltage with respect to ground ...................... –0.5 V to +7.0 V

Input signal with respect to ground .................................. –3.0 V to +7.0 V

Signal applied to high impedance output ......................... –3.0 V to +7.0 V

Output current into low outputs ....................................................... 25 mA

Latchup current ......................................................................... > 400 mA

T

ABLE

1. C

ONTROL

E

NCODING

Length Code

Mode = 0 Mode = 1

Delay

L

3

0

1

L

2

0

1

0

1

L

1

L

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Y

3-0

Y

7-4

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Delay

Y

3-0

Y

7-4

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

O

PERATING

C

ONDITIONS

To meet specified electrical and switching characteristics

Mode

Active Operation, Com.

Active Operation, Mil.

Temperature Range

0°C to +70°C

–55°C to +125°C

Supply Voltage

4.75 V £

V

CC

£ 5.25 V

4.50 V £

V

CC

£ 5.50 V

E

LECTRICAL

C

HARACTERISTICS

Over Operating Conditions (Note 4)

Symbol

V

OH

V

OL

V

IH

V

IL

I

IX

I

CC1

I

CC2

Parameter

Output High Voltage

Output Low Voltage

Input High Voltage

Input Low Voltage

Input Current

V

CC

Current, Dynamic

V

CC

Current, Quiescent

(Note 3)

Test Condition

V

CC

= Min.,

I

OH

= –12 mA

V

CC

= Min.,

I

OL

= 24 mA

Min

2.4

Typ

Max

Unit

V

0.5

2.0

0.0

V

CC

0.8

±20

10

20

1.0

V

µA

mA

Ground

≤

V

IN

≤

V

CC

(Note 12)

(Notes 5, 6)

(Note 7)

Pipeline Registers

2

03/27/2000–LDS.11-L

432109876543210987654321

*D

ISCONTINUED

S

PEED

G

RADE

Symbol

4321098765432121098765432109876543210987654321

Min

6543210987654321

Min

DEVICES INCORPORATED

S

WITCHING

W

AVEFORMS

M

ILITARY

O

PERATING

R

ANGE

(–55°C to +125°C)

Notes 9, 10 (ns)

C

OMMERCIAL

O

PERATING

R

ANGE

(0°C to +70°C)

Notes 9, 10 (ns)

SWITCHING CHARACTERISTICS

L

3-0

MODE

t

HL

t

SL

t

HD

t

SD

t

PW

t

PD

t

HL

t

SL

t

HD

t

SD

t

PW

t

PD

CLK

D

7-0

Y

7-0

Parameter

L

3-0

, MODE Hold Time

L

3-0

, MODE Setup Time

Data Hold Time

Data Setup Time

Clock Pulse Width

Output Delay

L

3-0

, MODE Hold Time

L

3-0

, MODE Setup Time

Data Hold Time

Data Setup Time

Clock Pulse Width

Output Delay

t

SD

t

SL

t

HD

t

HL

t

PW

3

t

PD

4/8-bit Variable Length Shift Register

25

15

20

15

25

20

2

30*

25*

Max

30

25

t

PW

Min

10

12

10

12

10

L10C11–

25*

L10C11–

20

2

0

2

0

Pipeline Registers

Max

25

20

Min

10

12

10

03/27/2000–LDS.11-L

8

0

L10C11

20*

15

Max

20

15

L10C11

DEVICES INCORPORATED

4/8-bit Variable Length Shift Register

NOTES

1. Maximum Ratings indicate stress

specifications only. Functional oper-

ation of these products at values be-

yond those indicated in the Operating

Conditions table is not implied. Expo-

sure to maximum rating conditions for

extended periods may affect reliability.

9. AC specifications are tested with

input transition times less than 3 ns,

output reference levels of 1.5 V (except

t

DIS

test), and input levels of nominally

0 to 3.0 V. Output loading may be a

resistive divider which provides for

specified

I

OH

and

I

OL

at an output

voltage of

V

OH

min and

V

OL

max

respectively. Alternatively, a diode

bridge with upper and lower current

sources of

I

OH

and

I

OL

respectively,

and a balancing voltage of 1.5 V may be

used. Parasitic capacitance is 30 pF

minimum, and may be distributed.

11. For the

t

ENA

test, the transition is

measured to the 1.5 V crossing point

with datasheet loads. For the

t

DIS

test,

the transition is measured to the

±200mV level from the measured

steady-state output voltage with

±10mA loads. The balancing volt-

age, V

TH

, is set at 3.5 V for Z-to-0

and 0-to-Z tests, and set at 0 V for Z-

to-1 and 1-to-Z tests.

2. The products described by this speci-

fication include internal circuitry de-

signedto protect the chipfrom damaging

substrate injection currents and accumu-

12. These parameters are only tested at

lations of static charge. Nevertheless,

the high temperature extreme, which is

conventional precautions should be ob-

the worst case for leakage current.

served during storage, handling, and use

F

IGURE

A. O

UTPUT

L

OADING

C

IRCUIT

of these circuits in order to avoid expo- This device has high-speed outputs ca-

sure to excessive electrical stress values. pable of large instantaneous current

pulses and fast turn-on/turn-off times.

3. This device provides hard clamping of As a result, care must be exercised in the

S1

transient undershoot and overshoot. In- testing of this device. The following

DUT

I

OL

put levels below ground or above

V

CC

measures are recommended:

V

TH

C

L

will be clamped beginning at –0.6 V and

I

OH

V

CC

+ 0.6 V. The device can withstand a. A 0.1 µF ceramic capacitor should be

indefinite operation with inputs in the installed between

V

CC

and Ground

range of –0.5 V to +7.0 V. Device opera- leads as close to the Device Under Test

F

IGURE

B. T

HRESHOLD

L

EVELS

tion will not be adversely affected, how- (DUT) as possible. Similar capacitors

t

ENA

t

DIS

ever, input current levels will be well in should be installed between device

V

CC

OE

1.5 V

excess of 100 mA.

and the tester common, and device

ground and tester common.

3.5V Vth

0

Z

4. Actual test conditions may vary from

1.5 V

V

OL

*

0.2 V

Z

0

those designated but operation is guar- b. Ground and

V

CC

supply planes

1

Z

anteed as specified.

must be brought directly to the DUT

0.2 V

V

OH

*

1.5 V

0V Vth

Z

1

socket or contactor fingers.

5. Supply current for a given application

V

OL

* Measured V

OL

with I

OH

= –10mA and I

OL

= 10mA

V

OH

* Measured V

OH

with I

OH

= –10mA and I

OL

= 10mA

can be accurately approximated by:

c. Input voltages should be adjusted to

compensate for inductive ground and

V

CC

NCV

2

F

noise to maintain required DUT input

levels relative to the DUT ground pin.

4

where

10. Each parameter is shown as a min-

imum or maximum value. Input re-

quirements are specified from the point

of view of the external system driving

the chip. Setup time, for example, is

6. Tested with all outputs changing ev- specified as a minimum since the exter-

ery cycle and no load, at a 5 MHz clock nal system must supply at least that

much time to meet the worst-case re-

rate.

quirements of all parts. Responses from

7. Tested with all inputs within 0.1 V of the internal circuitry are specified from

V

CC

or Ground, no load.

the point of view of the device. Output

8. These parameters are guaranteed delay, for example, is specified as a

maximum since worst-case operation of

but not 100% tested.

any device always provides data within

that time.

N = total number of device outputs

C = capacitive load per output

V = supply voltage

F = clock frequency

Pipeline Registers

4

03/27/2000–LDS.11-L

DEVICES INCORPORATED

ORDERING INFORMATION

7654321098765432121098765432109876543210987654321

Speed

20 ns

15 ns

–55°C to +125°C — MIL-STD-883 C

OMPLIANT

–55°C to +125°C — C

OMMERCIAL

S

CREENING

0°C to +70°C — C

OMMERCIAL

S

CREENING

24-pin — 0.3" wide

L10C11PC20

L10C11PC15

Plastic DIP

(P2)

D

0

D

1

D

2

D

3

L

0

L

1

V

CC

CLK

D

4

D

5

D

6

D

7

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

Y

0

Y

1

Y

2

Y

3

L

2

L

3

GND

MODE

Y

4

Y

5

Y

6

Y

7

5

4/8-bit Variable Length Shift Register

24-pin — 0.6" wide

D

0

D

1

D

2

D

3

L

0

L

1

V

CC

CLK

D

4

D

5

D

6

D

7

Discontinued Package

1

2

3

4

5

6

7

8

9

10

11

12

Plastic DIP

(P1)

Pipeline Registers

24

23

22

21

20

19

18

17

16

15

14

13

Y

0

Y

1

Y

2

Y

3

L

2

L

3

GND

MODE

Y

4

Y

5

Y

6

Y

7

03/27/2000–LDS.11-L

L10C11

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L10C11PC15 Related Products

	L10C11PC15	L10C11PC20
Description	Pipeline Register, 8-Bit, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24	Pipeline Register, 8-Bit, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
Is it Rohs certified?	incompatible	incompatible
Maker	LOGIC Devices	LOGIC Devices
Parts packaging code	DIP	DIP
package instruction	DIP,	DIP,
Contacts	24	24
Reach Compliance Code	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3
Other features	SELECTABLE DELAY LENGTH FROM 3 TO 18 STAGES; ICC SPECIFIED AT 5MHZ	SELECTABLE DELAY LENGTH FROM 3 TO 18 STAGES; ICC SPECIFIED AT 5MHZ
boundary scan	NO	NO
maximum clock frequency	66.66 MHz	50 MHz
External data bus width	8	8
JESD-30 code	R-PDIP-T24	R-PDIP-T24
JESD-609 code	e0	e0
length	30.861 mm	30.861 mm
low power mode	NO	NO
Humidity sensitivity level	3	3
Number of terminals	24	24
Maximum operating temperature	70 °C	70 °C
Output data bus width	8	8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	225	225
Certification status	Not Qualified	Not Qualified
Maximum seat height	4.572 mm	4.572 mm
Maximum slew rate	20 mA	20 mA
Maximum supply voltage	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	7.62 mm	7.62 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, PIPELINE REGISTER	DSP PERIPHERAL, PIPELINE REGISTER

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