32.768-kHz output (always active if VBATT is present).
Configurable clock output C.
Voltage supply.
Ground.
Reference crystal input or external reference clock input.
Reference crystal feedback.
Buffered reference clock output.
Configurable clock output D.
CPU frequency clock output.
Configurable clock output B.
Configurable clock output A.
Configurable clock output F.
CPU clock select input, bit 0.
CPU clock select input, bit 1.
CPU clock select input, bit 2. Optionally enables suspend feature when LOW.
Places outputs in three-state
[3]
condition and shuts down chip when LOW. Optionally, only
places outputs in three-state
[3]
condition and does not shut down chip when LOW.
Battery supply for 32.768-kHz circuit.
32.768 kHz crystal input.
Description
Notes
1. For best accuracy, use a parallel-resonant crystal, C
LOAD
≈
17 pF or 18 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
3. The CY2291 has weak pull downs on all outputs (except 32K). Hence, when a three-state condition is forced on the outputs, the output pins are pulled LOW.
4. If power is applied to VBATT, then a watch crystal (32.768 KHz) must be connected to the 32XIN and 32XOUT pins.
Document Number: 38-07189 Rev. *F
Page 3 of 16
CY2291
Output Configuration
The CY2291 has five independent frequency sources on-chip.
These are the 32-kHz oscillator, the reference oscillator, and
three Phase-locked loops (PLLs). Each PLL has a specific
function. The System PLL (SPLL) drives the CLKF output and
provides fixed output frequencies on the configurable outputs.
The SPLL offers the most output frequency divider options. The
CPU PLL (CPLL) is controlled by the select inputs (S0–S2) to
provide eight user-selectable frequencies with smooth slewing
between frequencies. The Utility PLL (UPLL) provides the most
accurate clock. It is often used for miscellaneous frequencies not
provided by the other frequency sources.
All configurations are EPROM programmable, providing short
sample and production lead times. Please refer to the application
note “Understanding the CY2291, CY2292, and CY2295” for
information on configuring the part.
CyClocks Software
CyClocks™ is an easy-to-use application that allows you to
configure any one of the EPROM programmable clocks offered
by Cypress. You may specify the input frequency, PLL and output
frequencies, and different functional options. Please note the
output frequency ranges in this data sheet when specifying them
in CyClocks to ensure that you stay within the limits. CyClocks
also has a power calculation feature that allows you to see the
power consumption of your specific configuration. CyClocks is a
sub-application within the CyberClocks™ software. You can
download a copy of CyberClocks for free on Cypress’s web site
at www.cypress.com.
Cypress FTG Programmer
The Cypress frequency timing generator (FTG) Programmers is
a portable programmer designed to custom program our family
of EPROM field programmable clock devices. The FTG
programmers connect to a PC serial port and allow users of
CyClocks software to quickly and easily program any of the
CY2291F, CY2292F, CY2071AF, and CY2907F devices. The
ordering code for the Cypress FTG Programmer is CY3670.
Power Saving Features
The SHUTDOWN/OE input three-states the outputs when pulled
LOW (the 32-kHz clock output is not affected). If system
shutdown is enabled, a LOW on this pin also shuts off the PLLs,
counters, the reference oscillator, and all other active
components. The resulting current on the V
DD
pins are less than
50
μA
(for Commercial Temp. or 100
μA
for Industrial Temp.) plus
15
μA
max. for the 32-kHz subsystem and is typically 10
μA.
After
leaving shutdown mode, the PLLs have to re-lock. All outputs
except 32K have a weak pull down so that the outputs do not float
when three-stated.
[3]
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs except 32K can be shut off in nearly any
combination. The only limitation is that if a PLL is shut off, all
outputs derived from it must also be shut off. Suspending a PLL
shuts off all associated logic, while suspending an output simply
forces a three-state condition.
[2]
The CPUCLK can slew (transition) smoothly between 8 MHz and
the maximum output frequency (100 MHz at 5V/80 MHz at 3.3 V
for commercial temp. parts or 90 MHz at 5V/66.6 MHz at 3.3 V
for industrial temp. and for field-programmed parts). This feature
is extremely useful in “Green” PC and laptop applications, where
reducing the frequency of operation can result in considerable
power savings. This feature meets all 486 and Pentium®
processor slewing requirements.
Custom Configuration Request Procedure
The CY229x are EPROM-programmable devices that may be
configured in the factory or in the field by a Cypress Field
Application Engineer (FAE). The output frequencies requested
are matched as closely as the internal PLL divider and multiplier
options allow. All custom requests must be submitted to your
local Cypress FAE or sales representative. The method to use to
request custom configurations is:
Use CyClocks™ software. This software automatically
calculates the output frequencies that can be generated by the
CY229x devices and provides a print-out of final pinout which
can be submitted (in electronic or print format) to your local FAE
or sales representative. The CyClocks software is available free
of charge from the Cypress web site (http://www.cypress.com) or
from your local sales representative.
Once the custom request has been processed you receive a part
number with a 3-digit extension (for example, CY2292SC-128)
specific to the frequencies and pinout of your device. This is the
part number used for samples requests and production orders.
Document Number: 38-07189 Rev. *F
Page 4 of 16
CY2291
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Supply voltage .............................................–0.5 V to + 7.0 V
DC input voltage ..........................................–0.5 V to + 7.0 V
Storage temperature ................................ –65
°C
to +150
°C
Maximum soldering temperature (10 sec) .................. 260
Power-up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic)
Electrical Characteristics, Commercial 5.0 V
Parameter
V
OH
V
OL
V
OH–32
V
OL–32
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
I
BATT
Description
HIGH-level output voltage
LOW-level output voltage
32.768-kHz HIGH-level
output voltage
32.768-kHz LOW-level
output voltage
HIGH-level input voltage
[9]
LOW-level input voltage
[9]
Input HIGH current
Input LOW current
Output leakage current
V
DD
supply current
commercial
[10]
I
OH
= 4.0 mA
I
OL
= 4.0 mA
I
OH
= 0.5 mA
I
OL
= 0.5 mA
Except crystal pins
Except crystal pins
V
IN
= V
DD
– 0.5 V
V
IN
= +0.5 V
Three-state outputs
V
DD
= V
DD
Max., 5 V operation
CY2291/CY2291F
Conditions
Min
2.4
−
V
BATT
0.5
−
2.0
−
−
−
−
−
−
−
75
10
5
Typ
−
−
−
−
−
−
<1
<1
Max
−
0.4
−
0.4
−
0.8
10
10
250
100
50
15
Unit
V
V
V
V
V
V
μA
μA
μA
mA
μA
μA
V
DD
power supply current in Shutdown active,
shutdown mode
[10]
excluding V
BATT
V
BATT
power supply current V
BATT
= 3.0 V
Notes
5. Electrical parameters are guaranteed by design with these operating conditions, unless otherwise noted.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
7. Please refer to Whitepaper “Crystal Parameters Recommendation for Cypress Frequency Synthesizers” for information on AC-coupling the external input reference
clock.
8. The oscillator circuit is optimized for a crystal reference and for external reference clocks up to 20 MHz. For external reference clocks above 20 MHz, it is recommended
that a 150Ω pull up resistor to V
DD
be connected to the Xout pin.
9. Xtal inputs have CMOS thresholds.
10. Load = Max., V
IN
= 0V or V
DD
, Typical (–104) configuration, CPUCLK = 66 MHz. Other configurations vary. Power can be approximated by the following formula
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