TCO UP AND TCO DOWN OUTPUTS; SEPARATE UP/DOWN CLOCK
Counting direction
BIDIRECTIONAL
series
CMOS
JESD-30 code
R-GDIP-T16
length
19.43 mm
Load/preset input
YES
Logic integrated circuit type
BINARY COUNTER
Operating mode
SYNCHRONOUS
Number of digits
4
Number of functions
1
Number of terminals
16
Maximum operating temperature
85 °C
Minimum operating temperature
-40 °C
Package body material
CERAMIC, GLASS-SEALED
encapsulated code
DIP
Package shape
RECTANGULAR
Package form
IN-LINE
propagation delay (tpd)
400 ns
Maximum seat height
5.08 mm
Maximum supply voltage (Vsup)
15 V
Minimum supply voltage (Vsup)
3 V
Nominal supply voltage (Vsup)
5 V
surface mount
NO
technology
CMOS
Temperature level
INDUSTRIAL
Terminal form
THROUGH-HOLE
Terminal pitch
2.54 mm
Terminal location
DUAL
Trigger type
POSITIVE EDGE
width
7.62 mm
minfmax
2.5 MHz
MM74C193J Preview
MM54C192 MM74C192 Synchronous 4-Bit Up Down Decade Counter
MM54C193 MM74C193 Synchronous 4-Bit Up Down Binary Counter
February 1988
MM54C192 MM74C192
Synchronous 4-Bit Up Down Decade Counter
MM54C193 MM74C193
Synchronous 4-Bit Up Down Binary Counter
General Description
These up down counters are monolithic complementary
MOS (CMOS) integrated circuits The MM54C192 and
MM74C192 are BCD counters while the MM54C193 and
MM74C193 are binary counters
Counting up and counting down is performed by two count
inputs one being held high while the other is clocked The
outputs change on the positive-going transition of this clock
These counters feature preset inputs that are set when load
is a logical ‘‘0’’ and a clear which forces all outputs to ‘‘0’’
when it is at a logical ‘‘1’’ The counters also have carry and
borrow outputs so that they can be cascaded using no ex-
ternal circuitry
Features
Y
Y
Y
Y
Y
Y
Connection Diagram
Dual-In-Line Package
O
C
1995 National Semiconductor Corporation
TL F 5901
bs
ol
TL F 5901 – 1
Order Number MM54C192 MM74C192
MM54C193 or MM74C193
et
Top View
RRD-B30M105 Printed in U S A
e
High noise margin
1V guaranteed
Tenth power TTL compatible
Drive 2 LPTTL loads
Wide supply range
3V to 15V
Carry and borrow outputs for N-bit cascading
Asynchronous clear
High noise immunity
0 45 V
CC
(typ )
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
b
0 3V to V
CC
a
0 3V
Voltage at Any Pin
Operating Temperature Range (T
A
)
MM54C154
MM74C154
b
55 C to
a
125 C
b
40 C to
a
85 C
Storage Temperature Range (T
S
)
Maximum V
CC
Voltage
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Operating V
CC
Range
Lead Temperature (T
A
)
(Soldering 10 sec )
b
65 C to
a
150 C
18V
700 mW
500 mW
3V to 15V
260 C
DC Electrical Characteristics
Min
Symbol
CMOS TO CMOS
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
I
IN(1)
I
IN(0)
I
CC
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Supply Current
Parameter
Max limits apply across temperature range unless otherwise noted
Conditions
Min
Typ
Max
Units
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V I
O
e b
10
mA
V
CC
e
10V I
O
e b
10
mA
V
CC
e
5V I
O
e
10
mA
V
CC
e
10V I
O
e
10
mA
V
CC
e
15V V
IN
e
15V
V
CC
e
15V V
IN
e
0V
V
CC
e
15V
35
80
15
20
V
V
V
V
CMOS TO LPTTL INTERFACE
V
IN(1)
V
IN(0)
V
OUT(1)
V
OUT(0)
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
bs
ol
54C V
CC
e
4 5V
74C V
CC
e
4 75V
54C V
CC
e
4 5V
74C V
CC
e
4 75V
V
CC
b
1 5
V
CC
b
1 5
54C V
CC
e
4 5V I
O
e b
100
mA
74C V
CC
e
4 75V I
O
e b
100
mA
24
24
54C V
CC
e
4 5V I
O
e
360
mA
74C V
CC
e
4 75V I
O
e
360
mA
V
CC
e
5V V
IN(0)
e
0V
T
A
e
25 C V
OUT
e
0V
b
1 75
b
8
et
0 005
10
b
1 0
b
0 005
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
I
SOURCE
I
SINK
I
SINK
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
O
V
CC
e
10V V
IN(0)
e
0V
T
A
e
25 C V
OUT
e
0V
V
CC
e
5V V
IN(1)
e
5V
T
A
e
25 C V
OUT
e
V
CC
V
CC
e
10V V
IN(1)
e
10V
T
A
e
25 C V
OUT
e
V
CC
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
2
e
45
90
V
V
05
10
V
V
mA
mA
mA
0 05
300
V
V
08
08
V
V
V
V
04
04
V
V
mA
mA
mA
mA
1 75
8
AC Electrical Characteristics
Symbol
t
pd
t
pd
t
pd
t
S
t
W
t
W
t
pd0
t
pd1
t
W
f
MAX
t
r
t
f
C
IN
C
PD
Parameter
Propagation Delay Time to Q
from Count Up or Down
Propagation Delay Time to Q
Borrow from Count Down
Propagation Delay Time to
Carry from Count Up
Time Prior to Load that Data
Must be Present
Minimum Clear Pulse Width
Minimum Load Pulse Width
Propagation Delay Time to Q
from Load
Minimum Count Pulse Width
Maximum Count Frequency
Count Rise and Fall Time
Input Capacitance
Power Dissipation Capacitance
T
A
e
25 C C
L
e
50 pF unless otherwise noted
Conditions
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
V
CC
e
5V
V
CC
e
10V
Min
Typ
250
100
120
50
120
50
100
30
300
120
100
40
300
120
120
35
4
10
Max
400
160
200
80
200
80
160
50
480
190
160
65
480
190
200
80
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
et
V
CC
e
5V
V
CC
e
10V
(Note 2)
15
5
5
(Note 3)
100
TL F 5901 – 2
AC Parameters are guaranteed by DC correlated testing
Note 2
Capacitance is guaranteed by periodic testing
Note 3
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note
AN-90
Cascading Packages
bs
ol
3
Note 1
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
O
e
25
6
MHz
MHz
ms
ms
pF
pF
Guaranteed Noise Margin
as a Function of V
CC
TL F 5901 – 3
Timing Diagrams
MM54C192 MM74C192
Note 1
Clear ouptuts to zero
Note 2
Load (preset) to binary thirteen
Note 3
Count up to fourteen fifteen carry zero one and two
Note 4
Count down to one zero borrow fifteen fourteen and thirteen
MM54C193 MM74C193
O
Note 1
Clear ouptuts to zero
Note 2
Load (preset) to BCD seven
Note 3
Count up to eight nine carry zero one and two
Note 4
Count down to one zero borrow nine eight and seven
Note A
Clear overrides load data and count inputs
Note B
When counting up count down input must be high when counting down count-up input must be high
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