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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ
PA1722
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
The
µ
PA1722 is N-Channel MOS Field Effect
Transistor designed for DC/DC converters and power
management applications of notebook computers.
8
PACKAGE DRAWING (Unit : mm)
5
1,2,3 ; Source
; Gate
4
5,6,7,8 ; Drain
FEATURES
•
Low on-resistance
R
DS(on)1
= 21.0 mΩ MAX. (V
GS
= 10 V, I
D
= 4.5 A)
1.44
R
DS(on)2
= 29.0 mΩ MAX. (V
GS
= 4.5 V, I
D
= 4.5 A)
1.8 MAX.
1
5.37 MAX.
4
6.0 ±0.3
4.4
+0.10
–0.05
R
DS(on)3
= 32.0 mΩ MAX. (V
GS
= 4.0 V, I
D
= 4.5 A)
•
Low C
iss
: C
iss
= 980 pF TYP.
•
Built-in G-S protection diode
•
Small and surface mount package (Power SOP8)
0.8
0.15
0.05 MIN.
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
ORDERING INFORMATION
PART NUMBER
PACKAGE
Power SOP8
µ
PA1722G
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
Gate to Source Voltage (V
DS
= 0 V)
Drain Current (DC)
Drain Current (pulse)
Note1
Note2
V
DSS
V
GSS
I
D(DC)
I
D(pulse)
P
T
T
ch
T
stg
30
±20
±9
±36
2.0
150
–55 to +150
V
V
A
A
W
°C
°C
EQUIVALENT CIRCUIT
Drain
Total Power Dissipation (T
A
= 25°C)
Channel Temperature
Storage Temperature
Gate
Body
Diode
Notes 1.
PW
≤
10
µ
s, Duty Cycle
≤
1 %
2.
Mounted on ceramic substrate of 1200 mm x 2.2 mm
Remark
2
Gate
Protection
Diode
Source
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G13890EJ2V0DS00 (2nd edition)
Date Published April 2001 NS CP(K)
Printed in Japan
The mark
!
shows major revised points.
©
1998, 1999
µ
PA1722
ELECTRICAL CHARACTERISTICS (T
A
= 25 °C, All terminals are connected.)
CHARACTERISTICS
Drain to Source On-state Resistance
SYMBOL
R
DS(on)1
R
DS(on)2
R
DS(on)3
Gate to Source Cut-off Voltage
Forward Transfer Admittance
Drain Leakage Current
Gate to Source Leakage Current
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V
GS(off)
| y
fs
|
I
DSS
I
GSS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GS
Q
GD
V
F(S-D)
t
rr
Q
rr
TEST CONDITIONS
V
GS
= 10 V, I
D
= 4.5 A
V
GS
= 4.5 V, I
D
= 4.5 A
V
GS
= 4.0 V, I
D
= 4.5 A
V
DS
= 10 V, I
D
= 1 mA
V
DS
= 10 V, I
D
= 4.5 A
V
DS
= 30 V, V
GS
= 0 V
V
GS
= ±20 V, V
DS
= 0 V
V
DS
= 10 V
V
GS
= 0 V
f = 1 MHz
I
D
= 4.5 A
V
GS(on)
= 10 V
V
DD
= 15 V
R
G
= 10
Ω
I
D
= 9 A
V
DD
= 24 V
V
GS
= 10 V
I
F
= 9 A, V
GS
= 0 V
I
F
= 9 A, V
GS
= 0 V
di/dt = 100 A/
µ
s
980
320
125
20
80
60
30
20
2.3
6.0
0.84
35
45
1.5
5.0
MIN.
TYP.
14.0
19.0
22.0
2.0
9.2
10
±10
MAX.
21.0
29.0
32.0
2.5
UNIT
mΩ
mΩ
mΩ
V
S
µ
A
µ
A
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 SWITCHING TIME
TEST CIRCUIT 2 GATE CHARGE
D.U.T.
D.U.T.
R
L
PG.
R
G
R
G
= 10
Ω
V
DD
I
D
90 %
90 %
I
D
0 10 %
t
d(on)
t
on
t
r
t
d(off)
t
off
10 %
t
f
V
GS
I
G
= 2 mA
V
GS(on)
90 %
V
GS
Wave Form
R
L
V
DD
0
10 %
PG.
50
Ω
V
GS
0
τ
τ
= 1
µ
s
Duty Cycle
≤
1 %
I
D
Wave Form
2
Data Sheet G13890EJ2V0DS
µ
PA1722
TYPICAL CHARACTERISTICS (T
A
= 25 °C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
2.8
dT - Percentage of Rated Power - %
P
T
- Total Power Dissipation - W
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
Mounted on ceramic
substrate of
1200 mm
2
×
2.2 mm
100
80
60
40
20
2.4
2.0
1.6
1.2
0.8
0.4
0
20
40
60
80
0
20
40
60
80
100 120 140 160
100 120 140 160
T
A
- Ambient Temperature - ˚C
T
A
- Ambient Temperature - ˚C
!
100
FORWARD BIAS SAFE OPERATING AREA
R
DS(on)
Limited
(V
GS
=10V)
I
D(DC)
10
I
D(pulse)
10
0m
Remark
10
1m
ms
0
µ
s
Mounted on ceramicsubstrate of 1200 mm
×
2.2 mm
2
I
D
- Drain Current - A
10
s
Po
s
we
rD
1
iss
ipa
tio
nL
im
ite
d
0.1
T
A
= 25˚C
Single Pulse
1
10
100
0.01
0.1
V
DS -
Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1 000
r
th(t)
- Transient Thermal Resistance - ˚C/W
100
R
th(ch-A)
= 62.5˚C/W
10
1
0.1
0.01
100
µ
Mounted on ceramic substrate
of 1200 mm
2
x 2.2 mm
Single Pulse
T
A
= 25˚C
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
Data Sheet G13890EJ2V0DS
3
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