SD-14531
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has...
TM
PROGRAMMABLE SYNCHRO/RESOLVER-
TO-DIGITAL CONVERTER
FEATURES
•
Single +5 V Power Supply
•
Accuracy to 1.3 Arc-Minutes
•
Pin Programmable
Synchro/Resolver Input Option
•
Pin Programmable 14-Bit or
16-Bit Resolution
•
No 180° False Lock-up
•
Internal Synthesized Reference
•
Built-In-Test (BIT) Output
•
Low Power Consumption
•
Pin-for-Pin Replacement for
Natel’s 1006 and 1056
DESCRIPTION
The SD-14531 is a low-cost, high reliability, programmable synchro/
resolver-to-digital converter with pin programmable 14- or 16-bit res-
olution. Packaged in a 36-pin DDIP, the SD-14531 features Built-In-
Test (BIT) output.
The SD-14531 series accepts broadband inputs: 360 to 1 kHz, or 47
to 1 kHz. Other features include solid-state signal and reference iso-
lation and high common-mode rejection. The digital angle output from
the SD-14531 is a natural binary code, parallel positive logic and is
TTL/CMOS compatible. Synchronization to a computer is accom-
plished with the Converter Busy (CB) output and/or the Inhibit (INH)
input.
APPLICATIONS
Because of its high reliability, small size, and low power consumption,
the SD-14531 is ideal for military ground or avionics applications. All
models are available with MIL-PRF-38534 processing.
Designed with three-state output, the SD-14531 is especially well
suited for use with computer based systems. Among the many pos-
sible applications are radar and navigation systems, fire control sys-
tems, flight instrumentation and flight trainers or simulators.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7382
©
1992, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
LOS
S1
S2
S3
S4
SIN
θ
COS
θ
REF IN
RH
RL
BIT
LOS
e
REFERENCE
CONDITIONER
R
SYNTHESIZED
REF
BIT DETECT
VEL
PROGRAMMABLE
SYNCHRO/
RESOLVER
CONDITIONER
S
SR
R
HIGH
ACCURACY
CONTROL
TRANSFORMER
GAIN
e
SIN
(θ-φ)
DEMODULATOR
D
VEL
ERROR
PROCESSOR
T
VCO
U
E
1 LSB ANTIJITTER FEEDBACK
16 BIT CT
TRANSPARENT
LATCH
CB
U
16 BIT
UP/DOWN
COUNTER
T
2
DIGITAL
ANGLE
φ
50 ns DELAY
INH
Q
INHIBIT
TRANSPARENT
LATCH
INH
3 STATE
TTL BUFFER
16 BIT OUTPUT
TRANSPARENT
LATCH
3 STATE
TTL BUFFER
T
EDGE
TRIGGERED
LATCH
+8.6 V
ANALOG RETURN
V(+4.3 V)
VOLTAGE
DOUBLER
+5 V
HBE
BITS 1-8
BITS 9-16 LBE
14B
RESOLUTION
CONTROL
V
SD-14531
FIGURE 1. SD-14531 BLOCK DIAGRAM
TABLE 1. SD-14531 SPECIFICATIONS
Specifications apply over temperature range, power supply range, reference fre-
quency, and amplitude range; 15% signal amplitude variation, up to 10% har-
monic distortion in the reference, and up to 45° of signal to reference phase shift.
PARAMETER
RESOLUTION
ACCURACY
REPEATABILITY
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Range
Voltage Range
UNIT
Bits
Min
LSB
VALUE
14 or 16 (See note 1)
5.2, 2.6, 1.6, or 1.3 (See
note 3)
1 max
TABLE 1. SD-14531 SPECIFICATIONS (CONT.)
PARAMETER
DIGITAL INPUT/OUTPUT
(CONT.)
OUTPUTS:
Parallel Data
UNIT
VALUE
Bits
14 or 16 parallel lines;
natural binary angles, pos-
itive logic.
0.8 to 3.0 positive pulse;
leading edge initiates
counter update.
Converter Busy (CB)
µs
Hz
Hz
Vrms
47-1000 (60 Hz Unit)
360-1000 (400 Hz Unit)
4-130 (for 11.8 V or 90 V
signal input)
3-100 (for 1 V direct signal
input)
250k min
500k min
250 peak max
BIT
Drive Capability
Logic 1 for fault conditions.
50 pF + rated logic drive
Logic 0; 1 TTL load,
1.6 mA at 0.4 V max
Logic 1; 10 TTL loads,
0.4 mA at 2.8 V min High
Z;10 µA || 5 pF max
Logic 0; 100 mV max
driving CMOS
Logic 1; +5 V supply
minus 100 mV min
driving CMOS
+4.3 V nom
See TABLE 4.
mVrms 3.5 per LSB of error
mVrms 1.75 per LSB of error
mA
1
See TABLE 6.
Input Impedance:
!
Single Ended
!
Differential
Common Mode Range
SIGNAL INPUT
CHARACTERISTICS
(voltage options and minimum
input impedance )
Input Impedance Imbalance
!
Synchro mode
• Zin Line-to-Line
• Zin Each Line-to-Gnd
• Common Mode Range
!
Resolver mode
• Zin Single Ended
• Zin Differential
• Zin Each Line-to Gnd
• Common Mode Range
!
Direct (1.0 V
L
-
L
)
• Input Signal Type
Ohm
Ohm
V
%
V
Ohm
Ohm
V
V
Ohm
Ohm
Ohm
V
0.2 max
11.8 V
L
-
L
60k
30k
30 max
11.8 V
L
-
L
30k
60k
30k
30 max
90 V
L
-
L
500k
250k
180 max
ANALOG OUTPUT
Analog Return (V)
Velocity (VEL) (See note 2)
AC error (e)
!
14-Bit Mode
!
16-Bit Mode
Load
DYNAMIC CHARACTERISTICS
POWER SUPPLY
CHARACTERISTICS
Nominal Voltage
Voltage Tolerance
Max Voltage w/o Damage
Current
TEMPERATURE RANGES
Operating (-1XXX or -4XXX)
(-3XXX or -8XXX)
Storage
PHYSICAL CHARACTERISTICS
Type
Size
Weight
• Sin/Cos Voltage Range
• Max Voltage w/o Damage
• Input Impedance
Vrms
Ohm
Sin and Cos resolver signals
referenced to converter inter-
nal DC reference V.
1 V nominal, 1.15 V max.
15 V continuous
100 V Peak Transient
Zin > 20M || 10pf voltage
follower
V
%
V
mA
°C
°C
°C
+5
±10
+7
25 max+digital output load
-55 to +125
0 to 70
-65 to +150
36-Pin DDIP
1.9 x 0.78 x 0.21
(48 x 20 x 5.3)
0.7 max (20)
REFERENCE SYNTHESIZER
± Sig/Ref Phase Shift
DIGITAL INPUT/OUTPUT
Logic Type
INPUTS:
Deg
60 typ, 45 guaranteed
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading = 30 µA max.
Logic 0 inhibits Data stable
within 0.5 µs (pull up)
Logic 1 for 14 bits
Logic 0 for 16 Bits
(Pull-up current source to
+5 V || 5 pF max CMOS
transient protected)
Logic 0 enables
Data Valid within 150 ns
Logic 1 = High Z
Data High Z within 100 ns
Pull-down current source
to GND || 5 pF max CMOS
transient protected
in
(mm)
oz(g)
Inhibit (INH)
Resolution Control (14B)
(for Programmable Units
Only)
Enable Bits 1 to 8 (HBE)
Enable Bits 9 to 16 (LBE)
(9 to 14 for 14-bit mode)
TRANSFORMER
CHARACTERISTICS
(See ordering information for list of
Transformers.
Reference Transformers are Optional
for Both Solid-State and Voltage
Follower Input Options.)
400 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Voltage Range
Input Impedance
Breakdown Voltage to GND
SIGNAL TRANSFORMER
Carrier Frequency Range
Breakdown Voltage to GND
360 - 1000 Hz
18 - 130 V
40 kΩ min
1200 V peak
360-1000 Hz
700 V peak
Data Device Corporation
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3
SD-14531
TABLE 1. SD-14531 SPECIFICATIONS (CONT.)
PARAMETER
TRANSFORMER
CHARACTERISTICS (CONT.)
Minimum Input impedances
(Balanced)
90 V L-L
26 V L-L
11.8 V L-L
60 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common-Mode Voltage
Output Description
VALUE
accuracy of the converter. The control transformer performs the
following trigonometric computation:
sin(θ -
φ)
= sinθ cosφ - cosθ sinφ
Where:
θ
is angle theta representing the resolver shaft position
φ
is digital angle phi contained in the up/down counter
The tracking process consists of continually adjusting
φ
to make
(θ -
φ)
= 0, so that
φ
will represent the shaft position
θ.
The output of the demodulator is an analog DC level proportion-
al to sin(θ -
φ).
The error processor receives its input from the
demodulator and integrates this sin(θ -
φ)
error signal which then
drives the VCO. The VCO’s clock pulses are accumulated by the
up/down counter. The velocity voltage accuracy, linearity and off-
set are determined by the quality of the VCO. Functionally, the
up/down counter is an incremental integrator. Therefore, there
are two stages of integration which makes the converter a Type
II tracking servo.
In a Type II servo, the VCO always settles to a counting rate
which makes dφ/dt equal to dθ/dt without lag. The output data will
always be fresh and available as long as the maximum tracking
rate of the converter is not exceeded.
The reference conditioner is a comparator that produces the
square wave reference voltage which drives the demodulator. It’s
single-ended Input Z is 250k Ohms min, 500k Ohms differential.
SynchroZ
IN
(Z
SO
)
180
Ω
-
20 kΩ
ResolverZ
IN
100 kΩ
30 kΩ
30 kΩ
47 - 440 Hz
80 -138 V rms; 115 V rms
nominal resistive
600 kΩ min, resistive
500 V rms transformer isolated
+R (in phase with RH-RL) and -R
(in phase with RL- RH) derived
from op-amps. Short-Circuit proof.
3.0 V nominal riding on ground
reference V. Output Voltage level
tracks input level.
4 mA typ, 7 mA max from +15 V
supply.
47 - 440 Hz
10 -100 V rms L- L; 90 V rms
L- L nominal
148 kΩ min L- L balanced
resistive
±500 V rms, transformer isolated
Resolver output,
- Sine (- S) + Cosine (+C) derived
from op-amps. Short circuit proof.
1.0 V rms nominal riding on
ground reference V. Output volt-
age level tracks input level.
4 mA typ, 7 mA max from +15 V
supply.
Output Voltage
Power Required
Signal Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common-Mode Voltage
Output Description
Output Voltage
Power Required
SPECIAL FUNCTIONS
The synthesized reference section of the SD-14531 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals typically lead the refer-
ence signal (RH and RL) by about 6°. When an uncompensated
reference signal is used to demodulate the control transformer’s
output, quadrature voltages are not completely eliminated. In a
14-bit converter it is not necessary to compensate for the refer-
ence signal’s phase shift. A 6° phase shift will, however, cause
problems for the one minute accuracy converters. As shown in
FIGURE 1, the converter synthesizes its own cos(ωt +
α)
refer-
ence signal from the sinθ - cos(ωt +
α),
cosθ - cos(ωt +
α)
signal
inputs and from the cosωt reference input. The phase angle of
the synthesized reference is determined by the signal input. The
reference input is used to choose between the +180° and -180°
phases. The synthesized reference will always be exactly in
phase with the signal input, and quadrature errors will therefore
be eliminated. The synthesized reference circuit also eliminates
the 180° false error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
Notes:
(1) Pin Programmable.
(2) VEL polarity is negative voltage for positive angular rate.
(3) XX5 ordering option = ±1.3 minutes resolver mode, ±1.6 minutes synchro
mode (16-bit mode only).
THEORY OF OPERATION
The SD-14531 Series are small, 36-pin DDIP synchro-to-digital
hybrid converters. As shown in the block diagram (FIGURE 1),
the SD-14531 can be broken down into the following functional
parts: Signal Input Option, Converter, Analog Conditioner, Power
Supply Conditioner, and Digital Interface.
CONVERTER OPERATION
As shown in FIGURE 1, the converter section of the SD-14531
contains a high accuracy control transformer, demodulator, error
processor, voltage-controlled oscillator (VCO), up-down counter,
and reference conditioner. The converter produces a digital
angle which tracks the analog input angle to within the specified
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4
SD-14531
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Magnitude of Error=(Quadrature Voltage/F.S.signal) • tan(α)
and reset after the converter settles out. BIT will also change to logic
1 for an over-velocity condition, because the converter loop cannot
maintain input-output and/or if the converter malfunctions where it
cannot maintain the loop at a null. BIT will also be set for a Loss-of-
Signal (LOS) and/or a Loss-of-Reference (LOR).
PROGRAMMABLE RESOLUTION (14B, PIN 16)
Where:
Magnitude of Error is in radians,
Quadrature Voltage is in volts,
Full Scale signal is in volts,
α
= signal-to-REF phase shift.
An example of the magnitude of error is as follows:
Let:
Quadrature Voltage = 11.8 mV
Let:
F.S. signal = 11.8 V
Let:
α
= 6°
Then: Magnitude of Error = 0.35 min
≅
1 LSB in the 16th bit.
Note: Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the speed volt-
age which is determined by the following formula:
Speed Voltage=(rotational speed/carrier frequency) • F.S. signal
Where:
Speed Voltage is the quadrature due to rotation,
Rotational speed is the rps (rotations per second) of the
synchro or resolver,
Carrier frequency is the REF in Hz.
+V
S1-S3 = V
MAX
MAX
SINθ
Resolution is controlled by one logic input,14B. The resolution
can be changed during converter operation so the appropriate
resolution and velocity dynamics can be changed as needed. To
insure that a race condition does not exist between counting and
changing the resolution, input 14B is latched internally on the
trailing edge of CB (see FIGURE 2).
INTERFACING - INPUTS
SIGNAL INPUT OPTIONS
The SD-14531 series offers programmable synchro or resolver
inputs. In a synchro or resolver, shaft angle data is transmitted as
the ratio of carrier amplitudes across the input terminals.
Synchro signals, which are of the form sinθcosωt, sin(θ+120°)
In Phase with
RL-RH of Converter
and R2-R1 of CX.
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
BUILT-IN-TEST (BIT, PIN 15)
The Built-In-Test output (BIT) monitors the level of error (D) from the
demodulator. D represents the difference in the input and output
angles and ideally should be zero; if it exceeds approximately 180
LSBs (of the selected resolution) the logic level at BIT will change
from a logic 0 to logic 1. This condition will occur during a large step
-V
MAX
S3-S2 = V
S2-S1 = V
MAX
SIN(θ
+ 120°)
MAX
SIN(θ
+ 240°)
Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation
From Electrical Zero (EZ).
+V
S2-S4 = V
MAX
MAX
COS
θ
In Phase with
RH-RL of Converter
and R2-R4 of RX.
CB
0
360
30
90
150
210
270
330
θ
CW
(DEGREES)
14B
;;; ;;
0
µs
MIN
0.1
µs
MIN
-V
MAX
S3-S1 = V
MAX
SIN(θ)
Standard Resolver Control Transmitter (RX) Outputs as a Function of CW Rotation
From Electrical Zero (EZ) With R2-R4 Excited.
FIGURE 2. RESOLUTION CONTROL TIMING DIAGRAM
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FIGURE 3. SYNCHRO AND RESOLVER SIGNALS
SD-14531
FPGA/CPLD
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