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FST16212 24-Bit Bus Exchange Switch
July 1997
Revised April 2005
FST16212
24-Bit Bus Exchange Switch
General Description
The Fairchild Switch FST16212 provides 24-bits of high-
speed CMOS TTL-compatible bus switching or exchang-
ing. The low on resistance of the switch allows inputs to be
connected to outputs without adding propagation delay or
generating additional ground bounce noise.
The device operates as a 24-bit bus switch or a 12-bit bus
exchanger, which allows data exchange between the four
signal ports via the data-select terminals.
Features
s
4
:
switch connection between two ports.
s
Minimal propagation delay through the switch.
s
Low l
CC
.
s
Zero bounce in flow-through mode.
s
Control inputs compatible with TTL level.
Ordering Code:
Order Number
FST16212MEA
FST16212MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Truth Table
S2
L
L
L
L
H
H
H
H
S1
L
L
H
H
L
L
H
H
S0
L
H
L
H
L
H
L
H
A
1
Z
B
1
B
2
Z
Z
Z
B
1
B
2
A
2
Z
Z
Z
B
1
B
2
Z
B
2
B
1
A
1
A
1
Function
Disconnect
A
1
A
1
A
2
A
2
B
1
B
2
B
1
B
2
B
2
B
1
Pin Descriptions
Pin Name
S2, S1, S0
A
1
, A
2
B
1
, B
2
Description
Data-select inputs
Bus A
Bus B
Disconnect
B
1
, A
2
B
2
, A
2
© 2005 Fairchild Semiconductor Corporation
DS500038
www.fairchildsemi.com
FST16212
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Switch Voltage (V
S
)
DC Input Voltage (V
IN
) (Note 2)
DC Input Diode Current (l
IK
) V
IN
0V
DC Output (I
OUT
) Sink Current
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
0.5V to
7.0V
0.5V to
7.0V
0.5V to
7.0V
50mA
128mA
Recommended Operating
Conditions
(Note 3)
Power Supply Operating (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Input Rise and Fall Time (t
r
, t
f
)
Switch Control Input
Switch I/O
Free Air Operating Temperature (T
A
)
0nS/V to 5nS/V
0nS/V to DC
4.0V to 5.5V
0V to 5.5V
0V to 5.5V
/
100mA
65
q
C to
150
q
C
40
q
C to
85
q
C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3:
Unused control inputs must be held high or low. They may not float.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
I
I
I
OZ
R
ON
Parameter
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Input Leakage Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 5)
V
CC
(V)
4.5
4.0–5.5
4.0–5.5
5.5
0
5.5
4.5
4.5
4.5
4.0
I
CC
Quiescent Supply Current
Increase in I
CC
per Input
5.0V and T
A
25
q
C
T
A
Min
40
q
C to
85
q
C
Typ
(Note 4)
Max
Units
V
V
0.8
V
I
IN
Conditions
1.2
2.0
18mA
r
1.0
10
P
A
P
A
P
A
:
:
:
:
P
A
mA
0
d
V
IN
d
5.5V
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
5.5V
0V, I
IN
0V, I
IN
2.4V, I
IN
2.4V, I
IN
64mA
30mA
15mA
15mA
0
0
d
A, B
d
V
CC
r
1.0
4
4
8
14
7
7
12
20
3
2.5
5.5
5.5
V
CC
or GND, I
OUT
'
I
CC
One input at 3.4V
Other inputs at V
CC
or GND
Note 4:
Typical values are at V
CC
Note 5:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
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2
FST16212
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
Min
t
PHL
,t
PLH
t
PHL
,t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
BW
Prop Delay Bus to Bus (Note 6)
Prop Delay S to Bus
Output Enable Time, S to A or B
Output Disable Time S to A or B
1.5
1.5
1.0
250
C
L
40
q
C to
85
q
C,
RD
500
:
4.0V
Max
0.25
7.5
8.0
9.0
ns
ns
ns
ns
MHz
V
I
V
I
V
I
V
I
8.5
V
I
V
I
R
L
OPEN
OPEN
7V for t
PZL
OPEN for t
PZH
7V for t
PLZ
OPEN for t
PHZ
50
:
Figures
1, 2
Figures
1, 2
Figures
1, 2
Figures
1, 2
Units
Conditions
V
CC
Min
Figure
No.
50pF, RU
4.5 – 5.5V
Max
0.25
7.0
7.5
3dB Bandwidth
Note 6:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Symbol
C
IN
C
I/O
Note 7:
T
A
(Note 7)
Parameter
Typ
3
10
Max
Units
pF
pF
V
CC
V
CC
5.0V
5.0V, S0, S1, or S2 GND
Conditions
Control pin Input Capacitance
Input/Output Capacitance
25
q
C, f
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50
:
source terminated in 50
:
Note: C
L
includes load and stray capacitance
Note Input PRR
1.0 MHz, t
W
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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FST16212
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS56A
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4
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