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PIC16F18345T-H/SS

Description
RISC Microcontroller, FLASH, CMOS, PDSO20
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size6MB,498 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

PIC16F18345T-H/SS Overview

RISC Microcontroller, FLASH, CMOS, PDSO20

PIC16F18345T-H/SS Parametric

Parameter NameAttribute value
MakerMicrochip
package instructionSSOP-20
Reach Compliance Codecompliant
Has ADCYES
Address bus width
maximum clock frequency32 MHz
DAC channelYES
DMA channelNO
External data bus width
JESD-30 codeR-PDSO-G20
length7.2 mm
Number of I/O lines18
Number of terminals20
On-chip program ROM width14
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
ROM programmabilityFLASH
Filter levelTS 16949
Maximum seat height2 mm
surface mountYES
technologyCMOS
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width5.3 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC

PIC16F18345T-H/SS Preview

PIC16(L)F18325/18345
Full-Featured, Low Pin Count Microcontrollers with XLP
Description
PIC16(L)F18325/18345 microcontrollers feature Analog, Core Independent Peripherals and Communication
Peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications.
The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,
PWM and communications) to add flexibility to the application design.
Core Features
• C Compiler Optimized RISC Architecture
• Only 48 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-bit Timers
• Up to Three 16-bit Timers
• Low-Current Power-on Reset (POR)
• Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Extended Watchdog Timer (WDT) with Dedicated
On-Chip Oscillator for Reliable Operation
• Programmable Code Protection
Power-Saving Functionality
• IDLE mode: ability to put the CPU core to Sleep
while internal peripherals continue operating from
the system clock
• DOZE mode: ability to run the CPU core slower
than the system clock used by the internal periph-
erals
• SLEEP mode: Lowest Power Consumption
• Peripheral Module Disable (PMD): peripheral
power disable hardware module to minimize
power consumption of unused peripherals
Digital Peripherals
• Configurable Logic Cell (CLC):
- Four CLCs
- Integrated combinational and sequential logic
• Complementary Waveform Generator (CWG):
- Two CWGs
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Capture/Compare/PWM (CCP) modules:
- Four CCPs
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• Pulse-Width Modulators (PWM)
- Two 10-bit PWMs
• Numerically Controlled Oscillator (NCO):
- Precision linear frequency generator (@50%
duty cycle) with 0.0001% step size of source
input clock
- Input Clock: 0 Hz < F
NCO
< 32 MHz
- Resolution: F
NCO
/2
20
• Serial Communications:
- EUSART
- RS-232, RS-485, LIN compatible
- Auto-Baud Detect, auto-wake-up on start
- Master Synchronous Serial Port (MSSP)
- SPI
- I
2
C, SMBus, PMBus™ compatible
• Data Signal Modulator (DSM):
- Modulates a carrier signal with digital data to
create custom carrier synchronized output
waveforms
Memory
14 Kbytes Program Flash Memory
1 KB Data SRAM Memory
256B of EEPROM
Direct, Indirect and Relative Addressing Modes
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF18325/18345)
- 2.3V to 5.5V (PIC16F18325/18345)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
eXtreme Low-Power (XLP) Features
Sleep mode: 40 nA @ 1.8V, typical
Watchdog Timer: 250 nA @ 1.8V, typical
Secondary Oscillator: 300 nA @ 32 kHz
Operating Current:
- 8 A @ 32 kHz, 1.8V, typical
- 37 A/MHz @ 1.8V, typical
2015-2019 Microchip Technology Inc.
DS40001795H-page 1
PIC16(L)F18325/18345
• Up to 18 I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
- Input level selection control (ST or TTL)
- Digital open-drain enable
• Peripheral Pin Select (PPS):
- I/O pin remapping of digital peripherals
• Timer modules:
- Timer0:
- 8/16-bit timer/counter
- Synchronous or asynchronous operation
- Programmable prescaler/postscaler
- Time base for capture/compare function
- Timer1/3/5 with gate control:
- 16-bit timer/counter
- Programmable internal or external clock
sources
- Multiple gate sources
- Multiple gate modes
- Time base for capture/compare function
- Timer2/4/6:
- 8-bit timers
- Programmable prescaler/postscaler
- Time base for PWM function
Flexible Oscillator Structure
• High-Precision Internal Oscillator:
- Software-selectable frequency range up to 32
MHz
- ±2% at nominal 4 MHz calibration point
• 4x PLL with External Sources
• Low-Power Internal 31 kHz Oscillator
(LFINTOSC)
• External Low-Power 32 kHz Crystal Oscillator
(SOSC)
• External Oscillator Block with:
- Three Crystal/Resonator modes up to
20 MHz
- Three External Clock modes up to 32 MHz
- Fail-Safe Clock Monitor
- Detects clock source failure
- Oscillator Start-up Timer (OST)
- Ensures stability of crystal oscillator
sources
Analog Peripherals
• 10-bit Analog-to-Digital Converter (ADC):
- 17 external channels
- Conversion available during Sleep
• Comparator:
- Two comparators
- Fixed Voltage Reference at non-inverting
input(s)
- Comparator outputs externally accessible
• 5-bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
DS40001795H-page 2
2015-2019 Microchip Technology Inc.
PIC16(L)F18325/18345
PIC16(L)F183XX Family Types
Program Flash
Memory (Kbytes)
Data Sheet Index
Program Flash
Memory (Words)
10-bit ADC (ch)
Idle and Doze
Y
Y
Y
Y
Y
Y
Y
Y
Data Memory
(bytes)
High-Speed/
Comparators
Data SRAM
(bytes)
10-bit PWM
Clock Ref
5-bit DAC
Timers
(8/16-bit)
EUSART
Debug
(1)
I
I
I
I
I
I
I
I
I
2
C/SPI
I/Os
(2)
CWG
NCO
DSM
Device
PIC16(L)F18313
PIC16(L)F18323
PIC16(L)F18324
PIC16(L)F18325
PIC16(L)F18344
PIC16(L)F18345
Note
(1)
(1)
(2)
(3)
(2)
(3)
2048
2048
4096
8192
4096
8192
3.5
3.5
7
14
28
7
14
28
256
256
256
256
256
256
256
256
256
256
512
6
5
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
2/1
2/1
4/3
4/3
4/3
4/3
4/3
4/3
2
2
4
4
4
4
4
4
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/1
1/1
1/1
2/2
2/2
1/1
2/2
2/2
2
2
4
4
4
4
4
4
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
12 11
12 11
1024 12 11
2048 12 15
512
18 17
1024 18 17
2048 18 21
PIC16(L)F18326
(4)
16384
PIC16(L)F18346
(4)
16384
1:
Debugging Methods: (I) – Integrated on Chip;
2:
One pin is input-only.
Data Sheet Index:
(Unshaded devices are described in this document.)
1:
DS40001799
PIC16(L)F18313/18323 Data Sheet, Full-Featured, Low Pin Count Microcontrollers with XLP
2:
DS40001800
PIC16(L)F18324/18344 Data Sheet, Full Featured, Low Pin Count Microcontrollers with XLP
3:
DS40001795
PIC16(L)F18325/18345 Data Sheet, Full Featured, Low Pin Count Microcontrollers with XLP
PIC16(L)F18326/18346 Data Sheet, Full Featured, Low Pin Count Microcontrollers with XLP
4:
DS40001839
Note:
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging
or contact your local sales office.
Pin Diagrams
FIGURE 1:
14-PIN PDIP, SOIC, TSSOP
V
DD
RA5
RA4
V
PP
/MCLR/RA3
RC5
RC4
RC3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
SS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
Note:
See
Table 1
for location of all peripheral functions.
2015-2019 Microchip Technology Inc.
PIC16(L)F18325
DS40001795H-page 3
PMD
Y
Y
Y
Y
Y
Y
Y
Y
CCP
CLC
PPS
XLP
PIC16(L)F18325/18345
FIGURE 2:
16-PIN UQFN, VQFN (4x4)
V
DD
NC
RA5
RA4
RA3/MCLR/V
PP
RC5
Note
1:
2:
See
Table 1
for location of all peripheral functions.
1
12 RA0/ICSPDAT
2
11 RA1/ICSPCLK
PIC16(L)F18325
3
10 RA2
4
9 RC0
5
6
7
8
It is recommended that the exposed bottom pad be connected to V
SS
, but must not be the main V
SS
connection to the device.
FIGURE 3:
20-PIN PDIP, SOIC, SSOP
RC4
RC3
RC2
RC1
16
15
14
13
NC
V
SS
V
DD
RA5
RA4
MCLR/V
PP
/RA3
RC5
RC4
RC3
RC6
RC7
RB7
1
2
3
20
19
18
V
SS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
RB4
RB5
RB6
PIC16(L)F18345
4
5
6
7
8
9
10
17
16
15
14
13
12
11
Note:
See
Table 2
for location of all peripheral functions.
FIGURE 4:
20-PIN UQFN, VQFN (4x4)
RA4
RA5
V
DD
V
SS
RA0/ICSPDAT
MCLR/V
PP
/RA3
RC5
RC4
RC3
RC6
1
15
2
14
3
PIC16(L)F18345
13
4
12
5
11
RC7
RB7
RB6
RB5
RB4
6
7
8
9
10
20
19
18
17
16
RA1/ICSPCLK
RA2
RC0
RC1
RC2
Note
1:
2:
See
Table 2
for location of all peripheral functions.
It is recommended that the exposed bottom pad be connected to V
SS
, but must not be the main V
SS
connection to the device.
DS40001795H-page 4
2015-2019 Microchip Technology Inc.
Pin Allocation Tables
TABLE 1:
14-Pin PDIP/SOIC/TSSOP
2015-2019 Microchip Technology Inc.
DS40001795H-page 5
14/16-PIN ALLOCATION TABLE (PIC16(L)F18325)
16-Pin UQFN
Comparator
Reference
EUSART
Interrupt
Pull-up
Timers
MSSP
CLKR
RA0
RA1
RA2
RA3
RA4
RA5
13
12
11
4
3
2
12
11
10
3
2
1
ANA0
ANA1
ANA2
ANA4
ANA5
V
REF
+
V
REF
-
C1IN0+
C1IN0-
C2IN0-
DAC1OUT
DAC1
REF
+
DAC1
REF
-
T0CKI
(1)
T1G
(1)
SOSCO
T1CKI
(1)
SOSCIN
SOSCI
T5CKI
(1)
T5G
(1)
T3G
(1)
T3CKI
(1)
CCP3
(1)
CWG1IN
(1)
CWG2IN
(1)
SS2
(1)
CLCIN3
(1)
IOC
IOC
INT
(1)
IOC
IOC
IOC
IOC
Y
Y
Y
Y
Y
Y
ICDDAT/
ICSPDAT
ICDCLK/
ICSPCLK
MCLR
V
PP
CLKOUT
OSC2
CLKIN
OSC1
V
DD
V
SS
Basic
CWG
PWM
I/O
(2)
NCO
DSM
DAC
ADC
CCP
CLC
PIC16(L)F18325/18345
RC0
RC1
RC2
RC3
RC4
RC5
V
DD
V
SS
Note
1:
2:
3:
4:
10
9
8
7
6
5
1
14
9
8
7
6
5
4
16
13
ANC0
ANC1
ANC2
ANC3
ANC4
ANC5
C2IN0+
C1IN1-
C2IN1-
C1IN2-
C2IN2-
C1IN3-
C2IN3-
MDCIN1
(1)
MDMIN
(1)
MDCIN2
(1)
CCP4
(1)
CCP2
(1)
CCP1
(1)
SCK1
(1)
SCL1
(1,3,4)
SDI1
(1)
SDA1
(1,3,4)
SS1
(1)
SCK2
(1)
SCL2
(1,3,4)
SDI2
(1)
SDA2
(1,3,4)
RX
(1)
CLCIN2
(1)
CLCIN0
(1)
CLCIN1
(1)
IOC
IOC
IOC
IOC
IOC
IOC
Y
Y
Y
Y
Y
Y
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
These pins are configured for I
2
C logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/
ST as selected by the INLVL register.

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