HY27US08121A-FEB datasheet, PDF

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HY27US08121A-FEB: DescriptionFlash, 64MX8, 30ns, PBGA63, 9 X 11 MM, 1 MM HEIGHT, 0.80 MM PITCH, FBGA-63; Categorystorage storage; File Size414KB，49 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY27US08121A-FEB Overview

Flash, 64MX8, 30ns, PBGA63, 9 X 11 MM, 1 MM HEIGHT, 0.80 MM PITCH, FBGA-63

HY27US08121A-FEB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	BGA
package instruction	VFBGA, BGA63,10X12,32
Contacts	63
Reach Compliance Code	unknown
ECCN code	3A991.B.1.A
Maximum access time	30 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PBGA-B63
JESD-609 code	e0
length	11 mm
memory density	536870912 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	4K
Number of terminals	63
word count	67108864 words
character code	64000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-25 °C
organize	64MX8
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA63,10X12,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
page size	512 words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Programming voltage	3.3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1 mm
Department size	16K
Maximum standby current	0.00005 A
Maximum slew rate	0.02 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	NO
type	SLC NAND TYPE
width	9 mm

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HY27US(08/16)121A Series

HY27SS(08/16)121A Series

512Mbit (64Mx8bit / 32Mx16bit) NAND Flash

Document Title

512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory

Revision History

Revision

No.

0.0

Initial Draft.

History

Draft Date

Sep. 2004

Remark

Preliminary

0.1

1) Correct part number ( change mode)

- 2A -> 1A (sequential row read : disable -> enable)

2) Correct Table.5 & Table 12

- Correct Command Set

- correct AC timing characteristics (tWP : 40 -> 25ns, tWH : 20 ->15ns)

3) Correct Summary description & page.7

- The cache feature is deleted in summary description.

Oct. 22. 2004

- Note.3 is deleted. (page.7)

4) Add System interface using CE don’t care (page. 38)

5) Change TSOP1, WSOP1,FBGA package dimension & figures.

- Change TSOP1, WSOP1, FBGA package mechanical data

- Change TSOP1, WSOP package figures

6) Correct TSOP1, WSOP1 Pin configuration

- 38th NC pin has been changed Lockpre (figure 2,3)

7) Add Bad block Management

1) LOCKPRE is changed to PRE

- Texts, Table and figures are changed.

2) Change Command set

- Read A,B are changed to Read1.

- Read C is changed to Read2.

3) Change AC, DC characterics

Preliminary

0.2

- tRB, tCRY, tCEH and tOH are added.

4) Correct Program time (max)

- before : 700us

- after

: 500us

5) Edit figures

- Address names are changed.

6) Change FBGA Package Dimension

- FD1 : 1.70(before) -> 0.90(after)

Mar. 08. 2005 Preliminary

Rev 1.3 / Jun. 2006

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