The Intel386 DX Microprocessor is an entry-level 32-bit microprocessor designed for single-user applications
and operating systems such as MS-DOS and Windows The 32-bit registers and data paths support 32-bit
addresses and data types The processor addresses up to four gigabytes of physical memory and 64 terabytes
(2 46) of virtual memory The integrated memory management and protection architecture includes address
translation registers multitasking hardware and a protection mechanism to support operating systems Instruc-
tion pipelining on-chip address translation ensure short average instruction execution times and maximum
system throughput
The Intel386 DX CPU offers new testability and debugging features Testability features include a self-test and
direct access to the page translation cache Four new breakpoint registers provide breakpoint traps on code
execution or data accesses for powerful debugging of even ROM-based systems
Object-code compatibility with all 8086 family members (8086 8088 80186 80188 80286) means the
Intel386 DX offers immediate access to the world’s largest microprocessor software base
231630– 49
Intel386
TM
DX Pipelined 32-Bit Microarchitecture
Intel386
TM
DX and Intel387
TM
DX are Trademarks of Intel Corporation
MS-DOS and Windows are Trademarks of MICROSOFT Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
December 1995
Order Number 231630-011
Intel386
TM
DX MICROPROCESSOR
32-BIT CHMOS MICROPROCESSOR
WITH INTEGRATED MEMORY MANAGEMENT
CONTENTS
1 PIN ASSIGNMENT
1 1 Pin Description Table
2 BASE ARCHITECTURE
2 1 Introduction
2 2 Register Overview
2 3 Register Descriptions
2 4 Instruction Set
2 5 Addressing Modes
2 6 Data Types
2 7 Memory Organization
2 8 I O Space
2 9 Interrupts
2 10 Reset and Initialization
2 11 Testability
2 12 Debugging Support
3 REAL MODE ARCHITECTURE
3 1 Real Mode Introduction
3 2 Memory Addressing
3 3 Reserved Locations
3 4 Interrupts
3 5 Shutdown and Halt
4 PROTECTED MODE ARCHITECTURE
4 1 Introduction
4 2 Addressing Mechanism
4 3 Segmentation
4 4 Protection
4 5 Paging
4 6 Virtual 8086 Environment
5 FUNCTIONAL DATA
5 1 Introduction
5 2 Signal Description
5 2 1 Introduction
5 2 2 Clock (CLK2)
5 2 3 Data Bus (D0 through D31)
5 2 4 Address Bus (BEO through BE3 A2 through A31)
5 2 5 Bus Cycle Definition Signals (W R D C M IO LOCK )
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