DPS128M8BJY-35B datasheet, PDF

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DPS128M8BJY-35B: DescriptionSRAM Module, 128KX8, 35ns, CMOS, CQCC48, HERMETIC SEALED, CERAMIC, J LEADED, MODULE, SLCC-48; Categorystorage storage; File Size811KB，10 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPS128M8BJY-35B Overview

SRAM Module, 128KX8, 35ns, CMOS, CQCC48, HERMETIC SEALED, CERAMIC, J LEADED, MODULE, SLCC-48

DPS128M8BJY-35B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	B&B Electronics Manufacturing Company
Parts packaging code	LCC
package instruction	AQCCJ, LDCC48,.51X.88
Contacts	48
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Maximum access time	35 ns
I/O type	COMMON
JESD-30 code	R-CQCC-J48
JESD-609 code	e0
memory density	1048576 bit
Memory IC Type	SRAM MODULE
memory width	8
Number of functions	1
Number of terminals	48
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX8
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	AQCCJ
Encapsulate equivalent code	LDCC48,.51X.88
Package shape	RECTANGULAR
Package form	CHIP CARRIER, PIGGYBACK
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Not Qualified
Filter level	38535Q/M;38534H;883B
Maximum seat height	3.6068 mm
Maximum standby current	0.0018 A
Minimum standby current	2 V
Maximum slew rate	0.16 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD

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1 Megabit High Speed CMOS SRAM

DPS128M8CnY/BnY, DPS128X8CA3/BA3

DESCRIPTION:

The DPS128M8CnY/BnY, DPS128X8CA3/BA3 High Speed SRAM

devices are a revolutionary new memory subsystem using Dense-Pac

Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).

Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages,

or mounted on a 50-pin PGA co-fired ceramic substrate. These devices

pack 1-Megabits of low-power CMOS static RAM in an area as small

as 0.463 in

, while maintaining a total height as low as 0.082 inches.

The SLCC devices contain an individual 128K x 8 SRAMs, each

packaged in a hermetically sealed SLCC, making the modules suitable

for commercial, industrial and military applications.

The DPS128M8BnY/DPS128X8BA3 has one active low Chip Enable

(CE) while the DPS128M8CnY/DPS128X8CA3 has an active low Chip

Enable (CE) and an active high Select Line (SEL).

By using SLCCs, the ‘’Stack’’ family of modules offer a higher board

density of memory than available with conventional through-hole,

surface mount or hybrid techniques.

SLCC

‘’I’’ Leaded

SLCC

FEATURES:

•

Organization Available: 128Kx8

Access Times: 20*, 25, 30, 35, 45ns

Fully Static Operation - No clock or refresh required

Single +5V Power Supply,

10% Tolerance

TTL Compatible

Common Data Inputs and Outputs

Low Data Retention Voltage: 2.0V min.

Packages Available:

48 - Pin SLCC

48 - Pin Straight Leaded SLCC

48 - Pin ‘’J’’ Leaded SLCC

48 - Pin Gullwing Leaded SLCC

50 - Pin PGA Dense-Stack

‘’J’’ Leaded

SLCC

Commercial only.

Dense-Stack

Gullwing

Leaded SLCC

30A097-31

REV. D

This document contains information on a product that is currently released

to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the

right to change products or specifications herein without prior notice.

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