PA7140T-25 datasheet, PDF - EEWORLD Datasheet

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PA7140T-25: DescriptionEE PLD, 25ns, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40; CategoryProgrammable logic devices Programmable logic; File Size272KB，6 Pages; ManufacturerIntegrated Circuit Systems（IDT ）

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PA7140T-25 Overview

EE PLD, 25ns, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40

PA7140T-25 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Integrated Circuit Systems（IDT ）
Parts packaging code	DIP
package instruction	DIP, DIP40,.6
Contacts	40
Reach Compliance Code	unknown
Other features	24 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
maximum clock frequency	35.7 MHz
JESD-30 code	R-PDIP-T40
JESD-609 code	e0
length	52.07 mm
Dedicated input times	12
Number of I/O lines	24
Number of entries	38
Output times	24
Number of terminals	40
Maximum operating temperature	70 °C
Minimum operating temperature
organize	12 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Programmable logic type	EE PLD
propagation delay	25 ns
Certification status	Not Qualified
Maximum seat height	3.81 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm

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PA7140T-25 Related Products

	PA7140T-25	PA7140T-20	PA7140TI-25
Description	EE PLD, 25ns, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40	EE PLD, 20ns, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40	EE PLD, 25ns, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）	Integrated Circuit Systems（IDT ）
Parts packaging code	DIP	DIP	DIP
package instruction	DIP, DIP40,.6	DIP, DIP40,.6	DIP, DIP40,.6
Contacts	40	40	40
Reach Compliance Code	unknown	unknown	unknown
Other features	24 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	24 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK	24 MACROCELLS; 2 EXTERNAL CLOCKS; SHARED INPUT/CLOCK
maximum clock frequency	35.7 MHz	45.4 MHz	35.7 MHz
JESD-30 code	R-PDIP-T40	R-PDIP-T40	R-PDIP-T40
JESD-609 code	e0	e0	e0
length	52.07 mm	52.07 mm	52.07 mm
Dedicated input times	12	12	12
Number of I/O lines	24	24	24
Number of entries	38	38	38
Output times	24	24	24
Number of terminals	40	40	40
Maximum operating temperature	70 °C	70 °C	85 °C
organize	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP	DIP
Encapsulate equivalent code	DIP40,.6	DIP40,.6	DIP40,.6
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE
power supply	5 V	5 V	5 V
Programmable logic type	EE PLD	EE PLD	EE PLD
propagation delay	25 ns	20 ns	25 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.81 mm	3.81 mm	3.81 mm
Maximum supply voltage	5.25 V	5.25 V	5.5 V
Minimum supply voltage	4.75 V	4.75 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V
surface mount	NO	NO	NO
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL
width	15.24 mm	15.24 mm	15.24 mm

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