Commercial/
Industrial
PA7140 PEEL
TM
Array
Features
s
Programmable Electrically Erasable Logic Array
s
Versatile Logic Array Architecture
- 24 I/Os, 14 inputs, 60 registers/latches
- Up to 72 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
High-Speed Commercial and Industrial Versions
- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (f
MAX
)
- Industrial grade available for 4.5 to 5.5V Vcc and -40
to +85 °C temperatures Ideal for Combinatorial,
Synchronous and Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, other wide-gate functions
CMOS Electrically Erasable Technology
,
-
Reprogrammable in 40-pin DIP
44-pin PLCC, and TQFP packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT PLACE Development Software
-Fitters for ABEL, CUPL and other software
-Programming support for by ICT PDS-3 and popular
third-party programmers
s
s
s
General Description
The PA7140 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free design-
ers from the limitations of ordinary PLDs by providing the
architectural flexibility and speed needed for today’s pro-
grammable logic designs. The PA7140 offers a versatile
logic array architecture with 24 I/O pins, 14 input pins and
60 registers/latches (24 buried logic cells, 12 input regis-
ters/latches, 24 buried I/O registers/latches). Its logic array
implements 100 sum-of-products logic functions divided
into two groups each serving 12 logic cells. Each group
shares half (60) of the 120 product-terms available for logic
cells.
The PA7140’s logic and I/O cells (LCCs, IOCs) are
extremely flexible with up to three output functions per cell
(a total of 72 for all 24 logic cells). Cells are configurable as
D, T, and JK registers with independent or global clocks,
resets, presets, clock polarity, and other features, making
the PA7140 suitable for a variety of combinatorial, synchro-
nous and asynchronous logic applications. The PA7140
supports speeds as fast as 13ns/20ns (tpdi/tpdx) and
66.6MHz (f
MAX
) at moderate power consumption 140mA
(100mA typical). Packaging includes 40-pin DIP and 44-pin
PLCC (see Figure 1). Development and programming sup-
port for the PA7140 is provided by ICT and popular third-
party development tool manufacturers.
Figure 1: Pin Configuration
Figure 2. Block Diagram
TQFP
44 43 42 41 40 39 38 37 36 35 34
33
1 Pin 1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
12 13 14 15 16 17 18 19 20 21 22
1 of 6
PA7140
Table 1. Absolute Maximum Ratings
Symbol
V
CC
V
I
, V
O
I
O
T
ST
T
LT
This device has been designed and tested for the recommended
operating conditions. Proper operation outside of these levels is not
guaranteed. Exposure to absolute maximum ratings may cause per-
manent damage.
Parameter
Supply Voltage
Voltage Applied to Any Pin
Output Current
Storage Temperature
Lead Temperature
Conditions
Relative to Ground
Relative to Ground
1
Per pin (I
OL
, I
OH
)
Ratings
-0.5 to + 7.0
-0.5 to V
CC
+ 0.6
±25
-65 to + 150
Unit
V
V
mA
°C
°C
Soldering 10 seconds
+300
Table 2. Operating Ranges
Symbol
V
CC
Parameter
Supply Voltage
Conditions
Commercial
Industrial
Commercial
Industrial
See Note 2
See Note 2
See Note 2
Min
4.75
4.5
0
-40
Max
5.25
5.5
+70
+85
20
20
250
Unit
V
T
A
T
R
T
F
T
RVCC
Ambient Temperature
Clock Rise Time
Clock Fall Time
V
CC
Rise Time
°C
ns
ns
ms
Table 3. D.C. Electrical Characteristics over the recommended operating conditions
Symbol
V
OH
V
OHC
V
OL
V
OLC
V
IH
V
IL
I
IL
I
OZ
I
SC
Parameter
Output HIGH Voltage - TTL
Output HIGH Voltage - CMOS
Output LOW Voltage - TTL
Output LOW Voltage - CMOS
Input HIGH Level
Input LOW Level
Input Leakage Current
Output Leakage Current
Output Short Circuit Current
4
Conditions
V
CC
= Min, I
OH
= -4.0mA
V
CC
= Min, I
OH
= -10µA
V
CC
= Min, I
OL
= 16mA
V
CC
= Min, I
OL
= -10µA
Min
2.4
V
CC
- 0.3
Max
Unit
V
V
0.5
0.15
2.0
-0.3
V
CC
+ 0.3
0.8
±10
±10
-30
-20
-25
I-25
100 (typ.)
18
-120
140
140
150
6
12
V
V
V
V
µA
µA
mA
V
CC
= Max, GND
≤
V
IN
≤
V
CC
I/O = High-Z, GND
≤
V
O
≤
V
CC
V
CC
= 5V, V
O
= 0.5V, T
A
= 25°C
V
IN
= 0V or V
CC
3,11
f = 25MHz
All outputs
disabled
4
ICC
11
V
CC
Current
mA
C
IN
7
C
OUT
7
Input Capacitance
5
Output Capacitance
5
T
A
= 25°C, V
CC
= 5.0V
@ f = 1 MHz
pF
pF
2 of 6
PA7140
Table 5. A.C Electrical Characteristics Combinatorial
Over the Operating Range
-20
Symbol
t
PDI
t
PDX
t
IA
t
AL
t
LC
t
LO
t
OD
, t
OE
t
OX
Parameter
6,12
Propagation delay Internal (t
AL + tLC)
Propagation delay External (t
IA
+ t
AL
+t
LC
+ t
LO
)
Input or I/O pin to array input
Array input to LCC
LCC input to LCC output
10
LCC output to output pin
Output Disable, Enable from LCC output
7
Output Disable, Enable from input pin
7
Min
Max
13
20
2
12
1
5
5
20
-25 / I -25
Min
Max
17
25
2
16
1
6
6
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Combinatorial Timing - Waveforms and Block Diagram
3 of 6
PA7140
Table 1. A.C. Electrical Characteristics Sequential
Symbol
t
SCI
t
SCX
t
COI
t
COX
t
HX
t
SK
t
AK
t
HK
t
SI
t
HI
t
PK
t
SPI
t
HPI
t
SD
t
HD
t
SDP
t
HDP
t
CK
t
CW
f
MAX
1
f
MAX
2
f
MAX
3
f
MAX
4
f
TGL
t
PR
t
ST
t
AW
t
RT
t
RTV
t
RTC
t
RW
t
RESET
Over the Operating Range
-20
Parameter
6,12
Internal set-up to system clock
8
- LCC
14
(t
AL
+ t
SK
+ t
LC
- t
CK
)
Input
16
(EXT.) set-up to system clock, - LCC (t
IA +
t
SCI)
System-clock to Array Int. - LCC/IOC/INC
14
(t
CK
+t
LC
)
System-clock to Output Ext. - LCC (t
COI
+ t
LO
)
Input hold time from system clock - LCC
LCC Input set-up to async. clock
13
- LCC
Clock at LCC or IOC - LCC output
LCC input hold time from system clock - LCC
Input set-up to system clock - IOC/INC
14
(t
SK
- t
CK
)
Input hold time from system clock - IOC/INC
14
(t
SK
- t
CK
)
Array input to IOC PCLK clock
Input set-up to PCLK clock
17
- IOC/INC (t
SK
-t
PK
-t
IA
)
Input hold from PCLK clock
17
- IOC/INC (t
PK
+t
IA
-t
SK
)
Input set-up to system clock - IOC/INC Sum-D
15
(t
IA
+ t
AL
+ t
LC
+ t
SK
- t
CK
)
Input hold time from system clock - IOC Sum-D
Input set-up to PCLK clock
(t
IA
+ t
AL
+ t
LC
+ t
SK
- t
PK
) - IOC Sum-D
Input hold time from PCLK clock - IOC Sum-D
System-clock delay to LCC/IOCINC
System-clock low or high pulse width
Max. system-clock frequency Int/Int 1/(t
SCI
+ t
COI
)
Max. system-clock frequency Ext/Int 1/(t
SCX
+ t
COI
)
Max. system-clock frequency Int/Ext 1/(t
SCI
+ t
COX
)
Max. system-clock frequency Ext/Ext 1/(t
SCX
+ t
COX
)
Max. system-clock toggle frequency 1/(t
CW
+ t
CW
)
LCC presents/reset to LCC output
Input to Global Cell present/reset (
tIA
+ t
AL
+ t
PR
)
Asynch. preset/reset pulse width
Input to LCC Reg-Type (RT)
LCC Reg-Type to LCC output register change
Input to Global Cell register-type change (t
RT
+ t
RTV
)
Asynch. Reg-Type pulse width
Power-on reset time for registers in clear state
2
10
5
8
8
1
9
7
66.6
58.8
50.0
45.4
71.4
1
15
0
10
10
0
7
0
6
0
1
1
4
0
5
9
Min
8
10
Max
-25 / I-25
Min
Max
11
14
Unit
ns
ns
7
12
0
1
1
4
0
6
8
14
ns
ns
ns
ns
ns
ns
ns
ns
11
0
12
13
0
9
0
7
8
52.6
45.4
40.0
35.7
62.5
2
20
8
10
2
12
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
µs
4 of 6
PA7140
Sequential Timing - Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V for
periods less than 20ns.
2. Test points for Clock and V
CC
in t
R
,t
F
,t
CL
,t
CH
, and t
RESET
are referenced
at 10% and 90% levels.
3. I/O pins are 0V or V
CC
.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless otherwise
specified).
7. t
OE
is measured from input transition to V
REF
±0.1V (See test loads at
end of Section 6 for V
REF
value). t
OD
is measured from input transition
to V
OH
-0.1V or V
OL
+0.1V.
8. DIP: “System-clock” refers to pin 1/21 high speed clocks. PLCC: “Sys-
tem-clock” refers to pin 2/24 high speed clocks.
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
12. Test loads are specified in Section 5 of this Data Book.
13. “Async. clock” refers to the clock from the Sum term (OR gate).
14. The “LCC” term indicates that the timing parameter is applied to the
LCC register. The “IOC” term indicates that the timing parameter is
applied to the IOC register. The “LCC/IOC” term indicates that the tim-
ing parameter is applied to both the LCC and IOC registers. The “LCC/
IOC/INC” term indicates that the timing parameter is applied to the
LCC, IOC and INC registers.
15. This refers to the Sum-D gate routed to the IOC register for an addi-
tional buried register
16. The term “Input” without any reference to another term refers to an
(external) input pin.
17. The parameter t
SPI
indicates that the PCLK signal to the IOC register is
always slower than the data from the pin or input by the absolute value
of (t
SK
-t
PK
-t
IA
). This means that no set-up time for the data from the
pin or input is required, i.e. the external data and clock can be sent to
the device simultaneously. Additionally, the data from the pin must
remain stable for t
HPI
time, i.e. to wait for the PCLK signal to arrive at
the IOC register.
18. Typical (typ) ICC is measured at T
A
=25° C, Freq = 25MHz, V
CC
=5V.
5 of 6
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