128Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
Release to Final Data Sheet.
1.1. Delete Preliminary.
2.2. Added Data Retention Characteristics.
Add 10ns part.
Draft Data
Aug. 5. 1998
Mar. 3. 1999
Remark
Preliminary
Final
Rev. 2.0
Mar. 3. 2000
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
FEATURES
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating KM681002C/CL-10 : 80mA(Max.)
KM681002C/CL-12 : 75mA(Max.)
KM681002C/CL-15 : 73mA(Max.)
KM681002C/CL-20 : 70mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention; L-ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM681002C/CLJ : 32-SOJ-400
KM681002C/CLT : 32-TSOP2-400CF
CMOS SRAM
GENERAL DESCRIPTION
The KM681002C is a 1,048,576-bit high-speed Static Random
Access Memory organized as 131,072 words by 8 bits. The
KM681002C uses 8 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM681002C is packaged
in a 400mil 32-pin plastic SOJ or TSOP2 forward.
128K x 8 Bit High-Speed CMOS Static RAM(5.0V Operating)
ORDERING INFORMATION
KM681002C/CL-10/12/15/20
KM681002CI/CLI-10/12/15/20
Commercial Temp.
Industrial Temp.
PIN CONFIGURATION
(Top View)
A
0
1
2
3
4
5
6
7
8
9
32 A
16
31 A
15
30 A
14
29 A
13
28 OE
27 I/O
8
26 I/O
7
FUNCTIONAL BLOCK DIAGRAM
A
1
A
2
A
3
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
Pre-Charge Circuit
CS
I/O
1
I/O
2
Vcc
SOJ/
TSOP2
25 Vss
24 Vcc
23 I/O
6
22 I/O
5
21 A
12
20 A
11
19 A
10
18
17
A
9
A
8
Row Select
Vss
Memory Array
512 Rows
256x8 Columns
I/O
3
10
I/O
4
11
WE
A
4
A
5
12
13
14
15
16
I/O
1
~I/O
8
Data
Cont.
CLK
Gen.
I/O Circuit
Column Select
A
6
A
7
PIN FUNCTION
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Pin Name
A
0
- A
16
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
CS
WE
OE
WE
CS
OE
I/O
1
~ I/O
8
V
CC
V
SS
N.C
-2-
Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
d
T
STG
T
A
T
A
Rating
-0.5 to Vcc+0.5V
-0.5 to 7.0
1
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
CMOS SRAM
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5**
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+ 0.5***
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA.
*** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
10ns
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Min. Cycle, CS=V
IH
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
I
OH1
=-0.1mA
Normal
L-ver.
Min
-2
-2
-
-
-
-
-
-
-
-
2.4
-
Max
2
2
80
75
73
70
30
5
0.5
0.4
-
3.95
V
V
V
mA
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
V
OH1
**
* The above parameters are also guaranteed at industrial temperature range.
** V
CC
=5.0V±5%, Temp.=25°C.
CAPACITANCE
*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
-3-
Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
*
The a
bove test conditions are also applied at industrial temperature range.
Value
0V to 3V
3ns
1.5V
See below
CMOS SRAM
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+5.0V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
480Ω
255
Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address
Chip Selection to Power Up Time
Chip Selection to Power Down-
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
KM681002C-10
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
10
KM681002C-12
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
6
-
-
12
KM681002C-15
Min
15
-
-
-
3
0
0
0
3
0
-
Max
-
15
15
7
-
-
7
7
-
-
15
KM681002C-20
Min
20
-
-
-
3
0
0
0
3
0
-
Max
-
20
20
9
-
-
9
9
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
-4-
Revision 2.0
March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM681002C-10
Min
10
7
0
7
7
10
0
0
5
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
KM681002C-12
Min
12
8
0
8
8
12
0
0
6
0
3
Max
-
-
-
-
-
-
-
6
-
-
-
KM681002C-15
Min
15
9
0
9
9
15
0
0
7
0
3
Max
-
-
-
-
-
-
-
7
-
-
-
KM681002C-20
Min
20
10
0
10
10
20
0
0
8
0
3
Max
-
-
-
-
-
-
-
9
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMOS SRAM
* The above parameters are also guaranteed at industrial temperature range.
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