Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MPC962304
Rev 0, 07/2004
3.3 V Zero Delay Buffer
The MPC962304 is a 3.3 V Zero Delay Buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom and other high-
performance applications. The MPC962304 uses an internal PLL and an
external feedback path to lock its low-skew clock output phase to the reference
clock phase, providing virtually zero propagation delay. The input-to-output
skew is guaranteed to be less than 250 ps and output-to-output skew is
guaranteed to be less than 200 ps.
Features
•
•
1:4 outputs LVCMOS zero-delay buffer
Zero input-output propagation delay, adjustable by the capacitive load on
FBK input
Multiple Configurations, See
Table 1. Available MPC962304
Configurations
Multiple low-skew outputs
– 200 ps max output-output skew
– 500 ps max device-device skew
Supports a clock I/O frequency range of 10 MHz to 133 MHz
Low jitter, 200 ps max cycle-cycle
8-pin SOIC package
Single 3.3 V supply
Ambient temperature range: –40°C to +85°C
Compatible with the CY2304
MPC962304
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-06
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•
•
•
•
•
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Functional Description
The MPC962304 has two banks of two outputs each. The MPC962304 PLL enters a power down state when there are no rising
edges on the REF input. During this state, all of the outputs are in tristate. When the PLL is turned off, there is less than 25
µA
of
current draw.
Multiple MPC962304 devices can accept and distribute the same input clock throughout the system. In this situation, the difference
between the output skews of two devices will be less than 500 ps.
The MPC962304 is offered in two configurations. In the -1 version, the reference frequency is reproduced by the PLL and provided
to the outputs.
The MPC962304-2 provides 1/2X and 2X the reference frequency at the output banks.
Block Diagram
Pin Configuration
8-pin SOIC
Top View
REF
CLKA1
CLKA2
GND
1
2
3
4
8
7
6
5
FBK
V
DD
CLKB2
CLKB1
FBK
REF
PLL
Extra Divider (–2)
CLKB1
CLKB2
CLKA1
CLKA2
/2
© Motorola, Inc. 2004
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MPC962304
Table 1. Available MPC962304 Configurations
Device
MPC962304-1
MPC962304-2
MPC962304-2
Feedback From
Bank A or Bank B
Bank A
Bank B
Bank A Frequency
Reference
Reference
2 X Reference
Bank B Frequency
Reference
Reference/2
Reference
Table 2. Pin Description
Pin
1
2
3
REF
1
CLKA1
2
CLKA2
2
GND
CLKB1
2
CLKB2
2
V
DD
FBK
Signal
Description
Input reference frequency, 5 V tolerant input
Clock output, Bank A
Clock output, Bank A
Ground
Clock output, Bank B
Clock output, Bank B
3.3 V supply
PLL feedback input
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4
5
6
7
8
1. Weak pull-down.
2. Weak pull-down on all outputs.
Table 3. Maximum Ratings
Characteristics
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage REF
Storage Temperature
Junction
Static Discharge Voltage (per MIL-STD-883, Method 3015)
Value
–0.5 to +3.9
–0.5 to V
DD
+0.5
–0.5 to 5.5
–65 to +150
150
>2000
Unit
V
V
V
°C
°C
V
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Freescale Semiconductor, Inc.
MPC962304
Table 4. Operating Conditions for MPC962304-X Industrial Temperature Devices
Parameter
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
1
Description
Min
3.0
–40
Max
3.6
85
30
15
7
Unit
V
°C
pF
pF
pF
1. Applies to both REF clock and FBK.
Table 5. Electrical Characteristics for MPC962304-X Industrial Temperature Devices
1
Parameter
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
2
Output HIGH Voltage
2
Power Down Supply Current
Supply Current
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (-1, -2)
I
OH
= -8 mA (-1, -2)
REF = 0 MHz
Unloaded outputs, 100 MHz,
Select inputs at V
DD
or GND
Unloaded outputs, 66-MHz REF
(-1, -2)
Unloaded outputs, 35-MHz REF
(-1, -2)
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
2.4
25.0
45.0
35.0
20.0
2.0
50.0
100.0
0.4
Test Conditions
Min
Max.
0.8
Unit
V
V
µA
µA
V
V
µA
mA
mA
mA
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PD mode)
I
DD
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MPC962304
Table 6. Switching Characteristics for MPC962304-X Industrial Temperature Devices
1
Parameter
t
1
Name
Output Frequency
Output Frequency
Duty Cycle
2
= t
2
÷
t
1
(-1, -2)
Duty Cycle
2
= t
2
÷
t
1
(-1, -2)
t
3
Rise Time
2
(-1, -2)
Rise Time
2
(-1, -2)
Test Conditions
30-pF load, all devices
15-pF load, all devices
Measured at 1.4 V, FOUT = 66.66 MHz
30-pF load
Measured at 1.4 V, FOUT < 50.0 MHz
15-pF load
Measured between 0.8 V and 2.0 V,
30-pF load
Measured between 0.8 V and 2.0 V,
15-pF load
Measured between 0.8 V and 2.0 V,
30-pF load
Measured between 0.8 V and 2.0 V,
15-pF load
2
Min
10
10
40.0
45.0
Typ
Max
100
133.3
60.0
55.0
2.50
1.50
2.50
1.50
200
200
400
Unit
MHz
MHz
%
%
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ms
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t
4
Fall Time
2
(-1, -2)
Fall Time
2
(-1, -2)
t
5
Output to Output Skew on
same Bank (-1, -2)
Output Bank A to Output
Bank B Skew (-1)
Output Bank A to Output
Bank B Skew (-2)
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of
devices
Measured at 66.67 MHz, loaded outputs,
15-pF load
Measured at 66.67 MHz, loaded outputs,
30-pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
0
0
t
6
t
7
t
J
Delay, REF Rising Edge to
FBK Rising Edge
2
±250
500
180
200
100
400
380
1.0
Device to Device Skew
2
Cycle to Cycle Jitter
2
(-1)
t
J
Cycle to Cycle Jitter
2
(-2)
Measured at 66.67 MHz, loaded outputs
30-pF load
Measured at 66.67 MHz, loaded outputs
15-pF load
t
LOCK
PLL Lock Time
2
Stable power supply, valid clocks presented
on REF and FBK pins
1. All parameters are specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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MPC962304
APPLICATIONS INFORMATION
V
CC
1.4 V
GND
V
CC
1.4 V
GND
t
5
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
t
6
FB_IN
CCLK
V
CC
V
CC
÷
2
GND
V
CC
V
CC
÷
2
GND
Figure 1. Output-to-Output Skew t
SK(O)
Figure 2. Static Phase Offset Test Reference
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V
CC
1.4 V
GND
t
2
t
1
DC = t
2
/t
1
x 100%
t
7
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
DEVICE 2
DEVICE 1
V
CC
V
CC
÷
2
GND
V
CC
V
CC
÷
2
GND
Figure 4. Device-to-Device Skew
Figure 3. Output Duty Cycle (DC)
V
CC
= 3.3 V
2.0
t
J
=
|t
N
–t
N+1
|
t
4
t
3
0.8
t
N
t
N+1
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
Figure 5. Cycle-to-Cycle Jitter
Figure 6. Output Transition Time Test Reference
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