MPC962304D-2 datasheet, PDF - EEWORLD Datasheet

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MPC962304D-2: Description962304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, PLASTIC, SOIC-8; Categorylogic logic; File Size378KB，8 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MPC962304D-2 Overview

962304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, PLASTIC, SOIC-8

MPC962304D-2 Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	SOIC
package instruction	SOP, SOP8,.25
Contacts	8
Reach Compliance Code	unknown
series	962304
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G8
length	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.008 A
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
power supply	3.3 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.4 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	3.9 mm
minfmax	133.3 MHz

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Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order number: MPC962304

Rev 0, 07/2004

3.3 V Zero Delay Buffer

The MPC962304 is a 3.3 V Zero Delay Buffer designed to distribute

high-speed clocks in PC, workstation, datacom, telecom and other high-

performance applications. The MPC962304 uses an internal PLL and an

external feedback path to lock its low-skew clock output phase to the reference

clock phase, providing virtually zero propagation delay. The input-to-output

skew is guaranteed to be less than 250 ps and output-to-output skew is

guaranteed to be less than 200 ps.

Features

•

1:4 outputs LVCMOS zero-delay buffer

Zero input-output propagation delay, adjustable by the capacitive load on

FBK input

Multiple Configurations, See

Table 1. Available MPC962304

Configurations

Multiple low-skew outputs

– 200 ps max output-output skew

– 500 ps max device-device skew

Supports a clock I/O frequency range of 10 MHz to 133 MHz

Low jitter, 200 ps max cycle-cycle

8-pin SOIC package

Single 3.3 V supply

Ambient temperature range: –40°C to +85°C

Compatible with the CY2304

MPC962304

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751-06

Freescale Semiconductor, Inc...

•

Functional Description

The MPC962304 has two banks of two outputs each. The MPC962304 PLL enters a power down state when there are no rising

edges on the REF input. During this state, all of the outputs are in tristate. When the PLL is turned off, there is less than 25

µA

current draw.

Multiple MPC962304 devices can accept and distribute the same input clock throughout the system. In this situation, the difference

between the output skews of two devices will be less than 500 ps.

The MPC962304 is offered in two configurations. In the -1 version, the reference frequency is reproduced by the PLL and provided

to the outputs.

The MPC962304-2 provides 1/2X and 2X the reference frequency at the output banks.

Block Diagram

Pin Configuration

8-pin SOIC

Top View

REF

CLKA1

CLKA2

GND

FBK

CLKB2

CLKB1

FBK

REF

PLL

Extra Divider (–2)

CLKB1

CLKB2

CLKA1

CLKA2

For More Information On This Product,

Go to: www.freescale.com

MPC962304D-2 Related Products

	MPC962304D-2	MPC962304D-1	MPC962304D-1R2	MPC962304D-2R2
Description	962304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, PLASTIC, SOIC-8	962304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, PLASTIC, SOIC-8	962304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, PLASTIC, SOIC-8	962304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.150 INCH, PLASTIC, SOIC-8
Maker	NXP	NXP	NXP	NXP
Parts packaging code	SOIC	SOIC	SOIC	SOIC
package instruction	SOP, SOP8,.25	SOP, SOP8,.25	SOP, SOP8,.25	SOP, SOP8,.25
Contacts	8	8	8	8
Reach Compliance Code	unknown	unknown	unknown	unknown
series	962304	962304	962304	962304
Input adjustment	STANDARD	STANDARD	STANDARD	STANDARD
JESD-30 code	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8	R-PDSO-G8
length	4.9 mm	4.9 mm	4.9 mm	4.9 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.008 A	0.008 A	0.008 A	0.008 A
Number of functions	1	1	1	1
Number of terminals	8	8	8	8
Actual output times	4	4	4	4
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	SOP	SOP
Encapsulate equivalent code	SOP8,.25	SOP8,.25	SOP8,.25	SOP8,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
power supply	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.4 ns	0.2 ns	0.2 ns	0.4 ns
Maximum seat height	1.75 mm	1.75 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	3.9 mm	3.9 mm	3.9 mm	3.9 mm
minfmax	133.3 MHz	133.3 MHz	133.3 MHz	133.3 MHz

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