DISCRETE SEMICONDUCTORS
DATA SHEET
book, halfpage
M3D186
BS108
N-channel enhancement mode
vertical D-MOS transistor
Product specification
Supersedes data of 1997 Jun 17
2001 May 18
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
FEATURES
•
Direct interface to C-MOS, TTL, etc.
•
High-speed switching
•
No secondary breakdown.
APPLICATIONS
•
Line current interruptor in telephone sets
•
Applications in relay, high-speed and line transformer
drivers.
DESCRIPTION
N-channel enhancement mode vertical D-MOS transistor
in a SOT54 (TO-92) package.
Fig.1
MAM150
BS108
PINNING - SOT54
PIN
1
2
3
source
gate
drain
DESCRIPTION
handbook, halfpage
d
1
2
3
g
s
Simplified outline (SOT54; TO-92) and
symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
V
GSth
I
D
R
DSon
drain-source voltage (DC)
gate-source threshold voltage
drain current (DC)
drain-source on-state resistance
PARAMETER
200
1.8
300
5
MAX.
V
V
mA
Ω
UNIT
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
V
DS
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
Note
1. Device mounted on a printed-circuit board, maximum lead length 4 mm; mounting pad for the drain lead minimum
10
×
10 mm.
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
T
amb
≤
25
°C;
note 1
open drain
CONDITIONS
−
−
−
−
−
−55
−
MIN.
MAX.
200
±20
300
1.2
1
+150
150
V
V
mA
A
W
°C
°C
UNIT
2001 May 18
2
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
Note
PARAMETER
CONDITIONS
VALUE
125
BS108
UNIT
K/W
thermal resistance from junction to ambient note 1
1. Device mounted on a printed-circuit board, maximum lead length 4 mm; mounting pad for the drain lead minimum
10
×
10 mm.
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)DSS
I
DSS
I
GSS
V
GSth
R
DSon
Y
fs
C
iss
C
oss
C
rss
PARAMETER
drain-source breakdown voltage
drain-source leakage current
gate-source leakage current
gate-source threshold voltage
drain-source on-state resistance
transfer admittance
input capacitance
output capacitance
reverse transfer capacitance
CONDITIONS
I
D
= 10
µA;
V
GS
= 0
V
DS
= 160 V; V
GS
= 0
V
GS
=
±20
V; V
DS
= 0
I
D
= 1 mA; V
GS
= V
DS
I
D
= 100 mA; V
GS
= 2.8 V
I
D
= 300 mA; V
DS
= 25 V
V
DS
= 25 V; V
GS
= 0;
f = 1 MHz
V
DS
= 25 V; V
GS
= 0;
f = 1 MHz
V
DS
= 25 V; V
GS
= 0;
f = 1 MHz
MIN.
200
−
−
0.4
−
200
−
−
−
TYP.
−
−
−
−
2.7
600
100
20
10
MAX.
−
1
±100
1.8
5
−
120
30
15
UNIT
V
µA
nA
V
Ω
mS
pF
pF
pF
Switching times (see Figs
2
and
3)
t
on
t
off
turn-on time
turn-off time
I
D
= 250 mA; V
DD
= 50 V;
V
GS
= 0 to 10 V
I
D
= 250 mA; V
DD
= 50 V;
V
GS
= 0 to 10 V
−
−
6
49
10
60
ns
ns
2001 May 18
3
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
BS108
handbook, halfpage
handbook, halfpage
90 %
VDD = 50 V
INPUT
10 %
90 %
10 V
0V
ID
50
Ω
MSA631
OUTPUT
10 %
ton
toff
MBB692
V
DD
= 50 V.
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
2001 May 18
4
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
PACKAGE OUTLINE
Plastic single-ended leaded (through hole) package; 3 leads
BS108
SOT54
c
E
d
A
L
b
1
D
2
e1
e
3
b
1
L1
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
5.2
5.0
b
0.48
0.40
b1
0.66
0.56
c
0.45
0.40
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
e
2.54
e1
1.27
L
14.5
12.7
L1
(1)
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54
REFERENCES
IEC
JEDEC
TO-92
EIAJ
SC-43
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
2001 May 18
5
京公网安备 11010802033920号
EEWORLD
