M393B5270DH0-CH9 datasheet, PDF

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M393B5270DH0-CH9: DescriptionDDR DRAM Module, 512MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, RDIMM-240; Categorystorage storage; File Size2MB，56 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/; Environmental Compliance

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M393B5270DH0-CH9 Overview

DDR DRAM Module, 512MX72, 0.255ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, RDIMM-240

M393B5270DH0-CH9 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SAMSUNG
package instruction	DIMM, DIMM240,40
Reach Compliance Code	compliant
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.255 ns
Other features	AUTO/SELF REFRESH; WD-MAX
Maximum clock frequency (fCLK)	667 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N240
length	133.35 mm
memory density	38654705664 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	240
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM240,40
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	30.15 mm
self refresh	YES
Maximum standby current	0.796 A
Maximum slew rate	2.92 mA
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4 mm

M393B5270DH0-CH9 Preview

Rev. 1.3, Jul. 2011

M393B5773DH0

M393B5273DH0

M393B5270DH0

M393B1K70DH0

M393B1K73DH0

M393B2K70DM0

240pin Registered DIMM

based on 2Gb D-die

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ

-1-

Registered DIMM

datasheet

History

Draft Date

Sep. 2010

Nov. 2010

Dec. 2010

May. 2011

Jun. 2011

Jul. 2011

Rev. 1.3

DDR3 SDRAM

Revision History

Revision No.

1.0

1.1

1.2

1.21

1.22

1.23

1.24

1.3

- First SPEC. Release

- Changed Input/Output capacitance on page 35.

- Changed 1866 speed bin table on page 39.

- Corrected typo.

- Changed timing parameters(Setup/Hold time)

Remark

Editor

S.H.Kim

J.Y.Lee

-2-

Registered DIMM

datasheet

Rev. 1.3

DDR3 SDRAM

Table Of Contents

240pin Registered DIMM based on 2Gb D-die

1. DDR3 Registered DIMM Ordering Information ............................................................................................................. 5

2. Key Features................................................................................................................................................................. 5

3. Address Configuration .................................................................................................................................................. 5

4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................ 6

5. Pin Description ............................................................................................................................................................. 7

6. ON DIMM Thermal Sensor ........................................................................................................................................... 7

7. Input/Output Functional Description.............................................................................................................................. 8

8. Pinout Comparison Based On Module Type................................................................................................................. 9

9. Registering Clock Driver Specification .......................................................................................................................... 10

9.1 Timing & Capacitance values .................................................................................................................................. 10

9.2 Clock driver Characteristics ..................................................................................................................................... 10

10. Function Block Diagram: ............................................................................................................................................. 11

10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... 11

10.2 4GB,512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) .................................................................. 12

10.3 4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ................................................................... 13

10.4 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ..................................................................... 14

10.5 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) .................................................................... 16

10.6 16GB, 2Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs) ................................................................... 17

11. Absolute Maximum Ratings ........................................................................................................................................ 22

11.1 Absolute Maximum DC Ratings............................................................................................................................. 22

11.2 DRAM Component Operating Temperature Range .............................................................................................. 22

12. AC & DC Operating Conditions................................................................................................................................... 22

12.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 22

13. AC & DC Input Measurement Levels .......................................................................................................................... 23

13.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 23

13.2 V

REF

Tolerances.................................................................................................................................................... 24

13.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 25

13.3.1. Differential Signals Definition ......................................................................................................................... 25

13.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 25

13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 26

13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 27

13.4 Slew Rate Definition for Single Ended Input Signals ............................................................................................. 27

13.5 Slew rate definition for Differential Input Signals ................................................................................................... 27

14. AC & DC Output Measurement Levels ....................................................................................................................... 28

14.1 Single Ended AC and DC Output Levels............................................................................................................... 28

14.2 Differential AC and DC Output Levels ................................................................................................................... 28

14.3 Single-ended Output Slew Rate ............................................................................................................................ 28

14.4 Differential Output Slew Rate ................................................................................................................................ 29

15. DIMM IDD specification definition ............................................................................................................................... 30

16. IDD SPEC Table ......................................................................................................................................................... 32

17. Input/Output Capacitance ........................................................................................................................................... 35

18. Electrical Characteristics and AC timing ..................................................................................................................... 36

18.1 Refresh Parameters by Device Density................................................................................................................. 36

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 36

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 36

18.3.1. Speed Bin Table Notes .................................................................................................................................. 40

19. Timing Parameters by Speed Grade .......................................................................................................................... 41

19.1 Jitter Notes ............................................................................................................................................................ 47

19.2 Timing Parameter Notes........................................................................................................................................ 48

20. Physical Dimensions................................................................................................................................................... 49

20.1 256Mbx8 based 256Mx72 Module (1 Rank) - M393B5773DH0 ............................................................................ 49

20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs................................................................ 49

-3-

Registered DIMM

datasheet

Rev. 1.3

DDR3 SDRAM

20.2 256Mbx8 based 512Mx72 Module (2 Ranks) - M393B5273DH0 .......................................................................... 50

20.2.1. x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs .............................................................. 50

20.3 512Mbx4 based 512Mx72 Module (1 Rank) - M393B5270DH0 ............................................................................ 51

20.3.1. x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs................................................................ 51

20.4 512Mbx4 based 1Gx72 Module (2 Ranks) - M393B1K70DH0 .............................................................................. 52

20.4.1. x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs .............................................................. 52

20.5 256Mbx8 based 1Gx72 Module (4 Ranks) - M393B1K73DH0 .............................................................................. 53

20.5.1. x72 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs .............................................................. 53

20.6 1Gbx4(DDP) based 2Gx72 Module (4 Ranks) - M393B2K70DM0........................................................................ 54

20.6.1. x72 DIMM, populated as four physical ranks of x4 DDR3 SDRAMs .............................................................. 54

20.6.2. Heat Spreader Design Guide ......................................................................................................................... 55

-4-

Registered DIMM

datasheet

Density

2GB

4GB

8GB

16GB

Organization

256Mx72

512Mx72

1Gx72

2Gx72

Component Composition

256Mx8(K4B2G0846D-HC##)*9

256Mx8(K4B2G0846D-HC##)*18

512Mx4(K4B2G0446D-HC##)*18

512Mx4(K4B2G0446D-HC##)*36

256Mx8(K4B2G0846D-HC##)*36

DDP 1Gx4(K4B4G0446D-MC##)*36

Rev. 1.3

DDR3 SDRAM

Number of

Rank

1. DDR3 Registered DIMM Ordering Information

Part Number

M393B5773DH0-CF8/H9/K0/MA

M393B5273DH0-CF8/H9/K0/MA

M393B5270DH0-CF8/H9/K0/MA

M393B1K70DH0-CF8/H9/K0/MA

M393B1K73DH0-CF8/H9

M393B2K70DM0-CF8/H9

Height

30mm

NOTE

1. "##" - F8/H9/K0/MA

2. F8(1066Mbps 7-7-7) / H9(1333Mbps 9-9-9) / K0(1600Mbps 11-11-11) / MA(1866Mbps 13-13-13)

- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)

2. Key Features

Speed

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

tRAS(min)

tRC(min)

DDR3-800

6-6-6

2.5

37.5

52.5

DDR3-1066

7-7-7

1.875

13.125

37.5

50.625

DDR3-1333

9-9-9

1.5

13.5

49.5

DDR3-1600

11-11-11

1.25

13.75

48.75

DDR3-1866

13-13-13

1.07

13.91

47.91

Unit

nCK

• JEDEC standard 1.5V ± 0.075V Power Supply

• V

DDQ

= 1.5V ± 0.075V

• 400MHz f

for 800Mb/sec/pin, 533MHz f

for 1066Mb/sec/pin, 667MHz f

for 1333Mb/sec/pin, 800MHz f

for 1600Mb/sec/pin,

933MHz f

for 1866Mb/sec/pin

• 8 independent internal bank

• Programmable CAS Latency: 6,7,8,9,10,11,13

• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

• Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866)

• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

write [either On the fly using A12 or MRS]

• Bi-directional Differential Data Strobe

• On Die Termination using ODT pin

• Average Refresh Period 7.8us at lower then T

CASE

85°C, 3.9us at 85°C < T

CASE

≤

95°C

• Asynchronous Reset

3. Address Configuration

Organization

512Mx4(2Gb) based Module

256Mx8(2Gb) based Module

1Gx4(4Gb DDP) based Module

Row Address

A0-A14

Column Address

A0-A9, A11

A0-A9

A0-A9, A11

Bank Address

BA0-BA2

Auto Precharge

A10/AP

-5-

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Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
package instruction	DIMM, DIMM240,40	DIMM, DIMM240,40	DIMM, DIMM240,40	DIMM, DIMM240,40	DIMM, DIMM240,40	DIMM, DIMM240,40	DIMM, DIMM240,40
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
access mode	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH; WD-MAX	AUTO/SELF REFRESH; WD-MAX	AUTO/SELF REFRESH; WD-MAX	AUTO/SELF REFRESH; WD-MAX	AUTO/SELF REFRESH; WD-MAX	AUTO/SELF REFRESH; WD-MAX	AUTO/SELF REFRESH; WD-MAX
Maximum clock frequency (fCLK)	667 MHz	800 MHz	933 MHz	533 MHz	533 MHz	933 MHz	667 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240
length	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm
memory density	38654705664 bit	38654705664 bit	38654705664 bit	38654705664 bit	77309411328 bit	77309411328 bit	77309411328 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	72	72	72	72	72	72	72
Number of functions	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1
Number of terminals	240	240	240	240	240	240	240
word count	536870912 words	536870912 words	536870912 words	536870912 words	1073741824 words	1073741824 words	1073741824 words
character code	512000000	512000000	512000000	512000000	1000000000	1000000000	1000000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
organize	512MX72	512MX72	512MX72	512MX72	1GX72	1GX72	1GX72
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM240,40	DIMM240,40	DIMM240,40	DIMM240,40	DIMM240,40	DIMM240,40	DIMM240,40
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
power supply	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192	8192
Maximum seat height	30.15 mm	30.15 mm	30.15 mm	30.15 mm	30.15 mm	30.15 mm	30.15 mm
self refresh	YES	YES	YES	YES	YES	YES	YES
Maximum standby current	0.796 A	0.846 A	0.846 A	0.756 A	0.972 A	1.062 A	1.012 A
Maximum slew rate	2.92 mA	3.06 mA	3.15 mA	2.53 mA	2.836 mA	3.51 mA	2.425 mA
Maximum supply voltage (Vsup)	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V	1.575 V
Minimum supply voltage (Vsup)	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V	1.425 V
Nominal supply voltage (Vsup)	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
surface mount	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	4 mm	4 mm	4 mm	4 mm	4 mm	4 mm	4 mm
Maximum access time	0.255 ns	0.225 ns	0.195 ns	0.3 ns	-	-	0.255 ns
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	260	NOT SPECIFIED	NOT SPECIFIED	-	-	-
Maximum time at peak reflow temperature	NOT SPECIFIED	40	NOT SPECIFIED	NOT SPECIFIED	-	-	-

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