8. Pinout Comparison Based On Module Type................................................................................................................. 9
10. Function Block Diagram: ............................................................................................................................................. 11
10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... 11
10.2 4GB,512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) .................................................................. 12
10.3 4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ................................................................... 13
10.4 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ..................................................................... 14
10.5 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) .................................................................... 16
10.6 16GB, 2Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs) ................................................................... 17
11. Absolute Maximum Ratings ........................................................................................................................................ 22
11.1 Absolute Maximum DC Ratings............................................................................................................................. 22
11.2 DRAM Component Operating Temperature Range .............................................................................................. 22
12. AC & DC Operating Conditions................................................................................................................................... 22
12.1 Recommended DC Operating Conditions (SSTL-15)............................................................................................ 22
13. AC & DC Input Measurement Levels .......................................................................................................................... 23
13.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 23
13.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 25
13.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 25
13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 26
13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 27
13.4 Slew Rate Definition for Single Ended Input Signals ............................................................................................. 27
13.5 Slew rate definition for Differential Input Signals ................................................................................................... 27
14. AC & DC Output Measurement Levels ....................................................................................................................... 28
14.1 Single Ended AC and DC Output Levels............................................................................................................... 28
14.2 Differential AC and DC Output Levels ................................................................................................................... 28
18. Electrical Characteristics and AC timing ..................................................................................................................... 36
18.1 Refresh Parameters by Device Density................................................................................................................. 36
18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 36
18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 36
18.3.1. Speed Bin Table Notes .................................................................................................................................. 40
19. Timing Parameters by Speed Grade .......................................................................................................................... 41
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