HYB18H512321BF-14 datasheet, PDF

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HYB18H512321BF-14: DescriptionSynchronous Graphics RAM, 16MX32, 0.25ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136; Categorystorage storage; File Size2MB，40 Pages; ManufacturerQIMONDA; Environmental Compliance

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HYB18H512321BF-14 Overview

Synchronous Graphics RAM, 16MX32, 0.25ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136

HYB18H512321BF-14 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	QIMONDA
Parts packaging code	DSBGA
package instruction	TFBGA, BGA136,12X17,32
Contacts	136
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.25 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	700 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B136
length	14 mm
memory density	536870912 bit
Memory IC Type	SYNCHRONOUS GRAPHICS RAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	136
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	16MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA136,12X17,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	4,8
Maximum standby current	0.235 A
Maximum slew rate	0.68 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	10 mm

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December 2007

HYB18H512321BF–11/12/14

HYB18H512321BF–08/10

512-Mbit GDDR3 Graphics RAM

GDDR3 Graphics RAM

RoHS compliant

Internet Data Sheet

Rev. 1.3

Internet Data Sheet

HYB18H512321BF

512-Mbit GDDR3

1.2

Description

The Qimonda 512-Mbit GDDR3 Graphics RAM is a high speed memory device, designed for high bandwidth intensive

applications like PC graphics systems. The chip’s 8 bank architecture is optimized for high speed.

HYB18H512321BF uses a double data rate interface and a 4

-pre fetch architecture. The GDDR3 interface transfers two 32

bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4

-pre fetch a single write or read access consists

of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clock-

cycle data transfers at the I/O pins.

Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively

in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized

per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are center-

aligned with data for write commands.

The HYB18H512321BF operates from a differential clock (CLK and CLK). Commands (addresses and control signals) are

registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is referenced to

both edges of RDQS.

In this document references to “the positive edge of CLK” imply the crossing of the positive edge of CLK and the negative edge

of CLK. Similarly, the “negative edge of CLK” refers to the crossing of the negative edge of CLK and the positive edge of CLK.

References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar

fashion.

Read and write accesses to the HYB18H512321BF are burst oriented. The burst length is fixed to 4 and 8 and the two least

significant bits of the burst address are “Don’t Care” and internally set to LOW. Accesses begin with the registration of an

ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident with the

READ or WRITE command are used to select the bank and the column location for the burst access. Each of the 8 banks

consists of 4096 row locations and 512 column locations. An AUTO PRECHARGE function can be combined with READ and

WRITE to provide a self-timed row precharge that is initiated at the end of the burst access. The pipe lined, multibank

architecture of the HYB18H512321BF allows for concurrent operation, thereby providing high effective bandwidth by hiding row

precharge and activation time.

The “On Die Termination” interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The

termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register.

The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (auto calibration) or

to 35, 40 or 45 Ohms.

Auto Refresh and Power Down with Self Refresh operations are supported.

An industrial standard PG–TFBGA–136 package is used which enables ultra high speed data transfer rates and a simple

upgrade path from former DDR Graphics SDRAM products.

Rev. 1.3, 2007-12

05292007-WAU2-UU95

HYB18H512321BF-14 Related Products

	HYB18H512321BF-14	HYB18H512321BF-11	HYB18H512321BF-08	HYB18H512321BF-12	HYB18H512321BF-10
Description	Synchronous Graphics RAM, 16MX32, 0.25ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136	Synchronous Graphics RAM, 16MX32, 0.22ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136	Synchronous Graphics RAM, 16MX32, 0.2ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136	Synchronous Graphics RAM, 16MX32, 0.22ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136	Synchronous Graphics RAM, 16MX32, 0.21ns, CMOS, PBGA136, 10 X 14 MM, GREEN, PLASTIC, MO-207IDR-Z, TFBGA-136
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Parts packaging code	DSBGA	DSBGA	DSBGA	DSBGA	DSBGA
package instruction	TFBGA, BGA136,12X17,32	TFBGA, BGA136,12X17,32	TFBGA, BGA136,12X17,32	TFBGA, BGA136,12X17,32	TFBGA, BGA136,12X17,32
Contacts	136	136	136	136	136
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Maximum access time	0.25 ns	0.22 ns	0.2 ns	0.22 ns	0.21 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	700 MHz	900 MHz	1200 MHz	800 MHz	1000 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B136	R-PBGA-B136	R-PBGA-B136	R-PBGA-B136	R-PBGA-B136
length	14 mm	14 mm	14 mm	14 mm	14 mm
memory density	536870912 bit	536870912 bit	536870912 bit	536870912 bit	536870912 bit
Memory IC Type	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM	SYNCHRONOUS GRAPHICS RAM
memory width	32	32	32	32	32
Number of functions	1	1	1	1	1
Number of ports	1	1	1	1	1
Number of terminals	136	136	136	136	136
word count	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
organize	16MX32	16MX32	16MX32	16MX32	16MX32
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA136,12X17,32	BGA136,12X17,32	BGA136,12X17,32	BGA136,12X17,32	BGA136,12X17,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
power supply	1.8 V	1.8 V	2 V	1.8 V	2 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES
Continuous burst length	4,8	4,8	4,8	4,8	4,8
Maximum standby current	0.235 A	0.35 A	0.41 A	0.32 A	0.38 A
Maximum slew rate	0.68 mA	0.8 mA	0.92 mA	0.74 mA	0.86 mA
Maximum supply voltage (Vsup)	1.9 V	1.9 V	2.1 V	1.9 V	2.1 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.9 V	1.7 V	1.9 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	2 V	1.8 V	2 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	10 mm	10 mm	10 mm	10 mm	10 mm
Maker	QIMONDA	-	QIMONDA	QIMONDA	QIMONDA

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