dsPIC33FJXXXGPX06A/X08A/X10A
16-bit Digital Signal Controllers (up to 256 KB Flash and
30 KB SRAM) with Advanced Analog
Operating Conditions
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
Timers/Output Compare/Input Capture
• Up to nine 16-bit timers/counters. Can pair up to
make four 32-bit timers.
• Eight Output Compare modules configurable as
timers/counters
• Eight Input Capture modules
Core: 16-bit dsPIC33F CPU
•
•
•
•
Code-efficient (C and Assembly) architecture
Two 40-bit wide accumulators
Single-cycle (MAC/MPY) with dual data fetch
Single-cycle mixed-sign MUL plus hardware
divide
Communication Interfaces
• Two UART modules (10 Mbps)
- With support for LIN 2.0 protocols and IrDA
®
• Two 4-wire SPI modules (15 Mbps)
• Up to two I
2
C™ modules (up to 1 Mbaud) with
SMBus support
• Up to two Enhanced CAN (ECAN) modules
(1 Mbaud) with 2.0B support
• Data Converter Interface (DCI) module with I
2
S
codec support
Clock Management
•
•
•
•
•
±2% internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast wake-up and start-up
Power Management
• Low-power management modes (Sleep, Idle,
Doze)
• Integrated Power-on Reset and Brown-out Reset
• 2.1 mA/MHz dynamic current (typical)
• 50
μA
I
PD
current (typical)
Input/Output
• Sink/Source up to 10 mA (pin specific) for stan-
dard V
OH
/V
OL
, up to 16 mA (pin specific) for
non-standard V
OH1
• 5V-tolerant pins
• Selectable open drain, pull-ups, and pull-downs
• Up to 5 mA overvoltage clamp current
• External interrupts on all I/O pins
Advanced Analog Features
• Two ADC modules:
- Configurable as 10-bit, 1.1 Msps with four
S&H or 12-bit, 500 ksps with one S&H
- 18 analog inputs on 64-pin devices and up to
32 analog inputs on 100-pin devices
• Flexible and independent ADC trigger sources
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC)
• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)
• Class B Safety Library, IEC 60730
Debugger Development Support
•
•
•
•
In-circuit and in-application programming
Two program and two complex data breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Trace and run-time watch
Packages
Type
QFN
TQFP
64
0.50
53
10x10x1
TQFP
80
0.50
69
12x12x1
TQFP
100
0.40
85
14x14x1
Pin Count
64
Contact Lead/Pitch
0.50
I/O Pins
53
Dimensions
9x9x0.9
Note:
All dimensions are in millimeters (mm) unless specified.
2009-2012 Microchip Technology Inc.
DS70593D-page 1
dsPIC33FJXXXGPX06A/X08A/X10A
dsPIC33F PRODUCT FAMILIES
The dsPIC33F General Purpose Family of devices
are ideal for a wide variety of 16-bit MCU embedded
applications. The controllers with codec interfaces are
well-suited for speech and audio processing
applications.
The device names, pin counts, memory sizes and
peripheral availability of each family are listed below,
followed by their pinout diagrams.
dsPIC33F General Purpose Family Controllers
Output Compare
Std. PWM
I/O Pins (Max)
(2)
Input Capture
16-bit Timer
Program
Flash
Pins
Memory
(Kbyte)
64
64
100
64
80
100
64
64
100
64
80
100
64
100
100
64
64
64
64
64
64
128
128
128
128
128
128
256
256
256
Enhanced
CAN™
Packages
PT, MR
PT, MR
PF, PT
PT, MR
PT
PF, PT
PT, MR
PT, MR
PF, PT
PT, MR
PT
PF, PT
PT, MR
PF, PT
PF, PT
Codec
Interface
UART
I
2
C™
1
2
2
2
2
2
1
2
2
2
2
2
2
2
2
ADC
Device
RAM
(Kbyte)
(1)
dsPIC33FJ64GP206A
dsPIC33FJ64GP306A
dsPIC33FJ64GP310A
dsPIC33FJ64GP706A
dsPIC33FJ64GP708A
dsPIC33FJ64GP710A
dsPIC33FJ128GP206A
dsPIC33FJ128GP306A
dsPIC33FJ128GP310A
dsPIC33FJ128GP706A
dsPIC33FJ128GP708A
dsPIC33FJ128GP710A
dsPIC33FJ256GP506A
dsPIC33FJ256GP510A
dsPIC33FJ256GP710A
Note 1:
2:
8
16
16
16
16
16
8
16
16
16
16
16
16
16
30
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 ADC, 18
ch
1 ADC, 18
ch
1 ADC, 32
ch
2 ADC, 18
ch
2 ADC, 24
ch
2 ADC, 32
ch
1 ADC, 18
ch
1 ADC, 18
ch
1 ADC, 32
ch
2 ADC, 18
ch
2 ADC, 24
ch
2 ADC, 32
ch
1 ADC, 18
ch
1 ADC, 32
ch
2 ADC, 32
ch
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SPI
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
0
0
2
2
2
0
0
0
2
2
2
1
1
2
53
53
85
53
69
85
53
53
85
53
69
85
53
85
85
RAM size is inclusive of 2 Kbytes DMA RAM.
Maximum I/O pin count includes pins shared by the peripheral functions.
DS70593D-page 2
2009-2012 Microchip Technology Inc.
FPGA/CPLD
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