EEWORLDEEWORLDEEWORLD

Part Number

Search

NMC-Q0201NPO8R010TRPF

Description
Multilayer Ceramic Chip Capacitors
File Size111KB,15 Pages
ManufacturerNIC
Websitehttps://www.niccomp.com
Download Datasheet View All

NMC-Q0201NPO8R010TRPF Overview

Multilayer Ceramic Chip Capacitors

Multilayer Ceramic Chip Capacitors
FEATURES
• HIGH Q FOR RF APPLICATIONS
• STABLE NPO CHARACTERISTICS OVER TEMPERATURE AND VOLTAGE
• HIGH VOLTAGE (UP TO 250VDC)
• EIA 0201, 0402 AND 0603 CASE SIZES
• IDEAL FOR WIRELESS DATA AND VOICE COMMUNICATIONS APPLICATIONS
WLANs, HIPERLAN, 802.11A, 802.11B, Wi-Fi, BLUETOOTH,TELEMATICS, PCS,
LMDS AND CELLULAR
SPECIFICATIONS
Capacitance Range
Capacitance Tolerance
Operating Temperature Range
Temperature Characteristics
Rated Voltage
Q Factor
insulation Resistance
Dielectric Withstanding Voltage
NPO
0.1pF ~ 47pF
±0.05pF(A), ±0.1pF(B), ±0.25pF(C), ±0.5pF(D)
±1%(F), ±2%(G), ±5% (J)
-55°C ~ +125°C
0 ± 30PPM/°C
6.3Vdc, 10Vdc, 25Vdc, 50Vdc, 100Vdc & 250Vdc
0201 & 0402 Q>400+20C (1MHz, +25°C)
0603 C<30pF Q>800+20C, C >30pF Q>1000
10,000 Megohms min. @ +25°C
100V < X 2.5RV, 250V x 2RV for 5 ± 1 seconds
NMC-Q Series
RoHS
Compliant
Includes all homogeneous materials
*See Part Number System for Details
S P tN b S t
f D t il
DIMENSIONS (mm)
EIA Case Size
Length (L)
Width (W)
Thickness (T)
Termination Width (P)
0201
0.6 ± 0.03
0.3 ± 0.03
0.33 max.
0.10 ~ 0.20
0402
1.0 ±0.05
0.5 ± 0.05
0.55 max.
0.15 ~ 0.30
0603
1.6 ±0.10
0.8 ± 0.10
0.87 max.
0.25 ~ 0.55
T
P
L
100% Sn over Ni barrier
P
W
PART NUMBER SYSTEM
NMC-Q 0603 NPO 100 J 50 TRP F
RoHS Compliant
Series
Tape & Reel (Punched carrier)
Voltage (Vdc)
Capacitance Tolerance Code (see chart)
Capacitance Code, expressed in pF,
rst 2 digits are
significant, 3rd digit is no. of zeros, “R” indicates
decimal for under 10pF
Temperature Characteristic
Size Code (see chart)
®
NIC COMPONENTS CORP.
www.niccomp.com
www.lowESR.com
www.RFpassives.com
www.SMTmagnetics.com
35
[AN-776 Application Note] Dual-Channel AD9981 Design Guidelines for UXGA Solutions
Introduction: With the AD9981, pixel clock rates exceeding 11-MHZ can be achieved using a two-chip "ping-pong" configuration....
EEWORLD社区 ADI Reference Circuit
xilinx FPGA LUT?
Does the LUT in Xilinx FPGA have a clock input pin?...
eeleader FPGA/CPLD
How to burn TMS320F28027 into FLASH using ccs5.2
How to burn TMS320F28027 into FLASH using ccs5.2...
jeffCXL DSP and ARM Processors
FPGA realizes digital tube counting
[i=s]This post was last edited by littleshrimp on 2021-12-18 15:52[/i]The function is similar to the counter in the mall where you can get a gold bar if you press the button for 10 seconds. Since ther...
littleshrimp Domestic Chip Exchange
Should we designers switch to management or sales in the future?
Should we designers switch to management or sales in the future?...
阿中 Talking about work
Personal learning experience in EEWORLD University Hall TI classroom
I am very happy to see the EEWORLD University Hall TI Classroom event. I watched this course very carefully and told you my feelings. :)This is my first time to contact with msp430. I think this cours...
supfool Microcontroller MCU

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2543  1524  1728  1387  1307  52  31  35  28  27 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号