Z8917520FSC datasheet, PDF - EEWORLD Datasheet

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Z8917520FSC: DescriptionIC 8-BIT, 20.48 MHz, MIXED DSP, PQFP100, QFP-100, Digital Signal Processor; CategoryThe embedded processor and controller Microcontrollers and processors; File Size441KB，68 Pages; ManufacturerZilog, Inc.; Websitehttps://www.zilog.com/

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Z8917520FSC Overview

IC 8-BIT, 20.48 MHz, MIXED DSP, PQFP100, QFP-100, Digital Signal Processor

Z8917520FSC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Zilog, Inc.
Parts packaging code	QFP
package instruction	QFP, QFP100,.7X.9
Contacts	100
Reach Compliance Code	unknown
Address bus width	16
barrel shifter	YES
bit size	8
boundary scan	NO
CPU series	Z8
maximum clock frequency	20.48 MHz
External data bus width	8
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
low power mode	YES
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.7X.9
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	256
rom(word)	24576
ROM programmability	MROM
Maximum seat height	3.1 mm
speed	20.4 MHz
Maximum slew rate	65 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, MIXED

Z8917520FSC Preview

RELIMINARY

RODUCT

PECIFICATION

Z89175

Z89176 (R

OMLESS

)

OICE

ROCESSING

ONTROLLERS

FEATURES

Device

Z89175

Z89176

ROM

(KB)

RAM*

(Bytes)

256

I/O

Lines

Voltage

Range

4.5V to 5.5V

Clock Speeds of 20.48 or 29.49 MHz

16-Bit Digital Signal Processor (DSP)

8K Word DSP Program ROM

512 Words On-Chip DSP RAM

8-Bit A/D Converter with up to 16 kHz Sample Rate

10-Bit PWM D/A Converter

Six Vectored, Prioritized Z8 Interrupts

Three Vectored, Prioritized DSP Interrupts

Two DSP Timers to Support Different A/D and D/A

Sampling Rates

IBM

PC-Based Development Tools

Developer’s Toolbox for T.A.M. Applications

Note:

*General-Purpose

Watch-Dog Timer and Power-On Reset

Improved Low Power Stop Mode

On-Chip Oscillator which Accepts a Crystal

or External Clock Drive

Improved Global Power-Down Mode

Low Power Consumption - 200 mW (typical)

Two Comparators

RAM and ROM Protect

On-Board Oscillator for 32.768 kHz Real-Time Clock

GENERAL DESCRIPTION

The Z89175/176 is a fully integrated, dual processor con-

troller designed for voice processing applications. The I/O

control processor is a Z8

with 24 KB of program memory,

two 8-bit counter/timers, and up to 47 I/O pins. The DSP is

a 16-bit processor with a 24-bit ALU and accumulator,

512x16 bits of RAM, single cycle instructions, and 8K

words of program ROM. The chip also contains a half-flash

8-bit A/D converter with up to a 16 kHz sample rate and a

10-bit PWM D/A converter. The sampling rates for the con-

verters are programmable. The precision of the 8-bit A/D

can be extended by resampling the data at a lower rate in

software. The Z8 and DSP processors are coupled by

mailbox registers and an interrupt system. DSP or Z8 pro-

grams can be directed by events in each other’s domain.

The Z89176 is the ROMless version of the Z89175. How-

ever, the on-chip DSP is not ROMless.

Notes:

All Signals with a preceding front slash, "/", are ac-

tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is

active Low, only).

Power connections follow conventional descriptions be-

low:

Connection

Power

Ground

Circuit

GND

Device

DS97TAD0100

PRELIMINARY

Z89175/Z89176

Voice Processing Controllers

Zilog

GENERAL DESCRIPTION

(Continued)

Z8 Core Processor

The on-chip Z8 is Zilog’s 8-bit microcontroller core with an

Expanded Register File to allow access to register-

mapped peripheral and I/O circuits. The Z8 offers a flexible

I/O scheme, an efficient register and address space struc-

ture and a number of ancillary features which makes it ide-

ally suited for high-volume processing, peripheral control-

lers and consumer applications.

For applications demanding powerful I/O capabilities, the

Z89175 provides 47 pins dedicated to input and output.

These I/O lines are grouped into six ports. Each port is

configurable under software control to provide timing, sta-

tus signals and parallel I/O with or without handshake.

Four basic memory resources for the Z8 are available to

support a wide range of configurations: Program Memory,

The Z8 core processor is supported by an efficient register

file that allows any of 256 on-board data and control regis-

ters to be either the source and/or the destination of almost

any instruction. This unique architecture eliminates tradi-

tional microprocessor Accumulator bottlenecks and per-

mits rapid content switching.

The Register File is composed of 236 bytes of general-pur-

pose registers, four I/O port registers, and 15 control and

status registers. The Expanded Register File consists of

mailbox registers, WDT mode register, DSP Control regis-

ter, Stop-Mode Recovery register, Port Configuration reg-

ister, and the control and data registers for Port 4 and Port

5. Some of these registers are shared with the DSP.

To unburden the software from supporting real-time prob-

lems such as counting/timing and data communication, the

Z8 offers two on-chip counter/timers with a large number

of user-selectable modes.

Watch-Dog Timer and Stop-Mode Recovery features are

software driven by setting specific bits in control registers.

STOP and HALT instructions support reduced power op-

eration. The low-power Stop Mode allows parameter infor-

mation to be stored in the register file if power fails. An ex-

ternal capacitor or battery will retain device memory and

power the 32 kHz timer.

DSP Coprocessor

The DSP coprocessor is a second generation, 16-bit two’s

complement CMOS Digital Signal Processor (DSP). Most

instructions, including multiply and accumulate, are ac-

complished in a single clock cycle. The processor contains

two on-chip data RAM blocks of 256 words, a 8K word pro-

gram ROM, 24-bit ALU, 16x16 multiplier, 24-bit Accumula-

tor, shifter, six-level stack, three vectored interrupts and

two inputs for conditional program jumps. Each RAM block

contains a set of four pointers which can be incremented

or decremented automatically to affect hardware looping

without software overhead. The data RAMs can be simul-

taneously addressed and loaded to the multiplier for a true

single-cycle scalar multiply.

Four external DSP registers are mapped into the expand-

ed register file of the Z8. Communication between the Z8

and the DSP occurs through those common registers

which form the mailbox registers.

The analog output is generated by a 10-bit resolution

Pulse Width Modulator. The PWM output is a digital signal

with CMOS output levels. The output signal has a resolu-

tion of 1 in 1024 with a sampling rate of 16 kHz (XTAL =

20.48 MHz). The sampling rate can be changed under

software control and can be set at 10 and 16 kHz. The dy-

namic range of the PWM is from 0 to 4V.

An 8-bit resolution half-flash A/D converter is provided.

The conversion is conducted with a sampling frequency of

16 kHz. (XTAL = 20.48 MHz) in order to provide oversam-

pling. The input signal is 4V peak to peak.

Two additional timers (Timer2 and Timer3) have been

added to support different sampling rates for the A/D and

D/A converters. These timers are free-running counters

that divide the crystal frequency to the appropriate sam-

pling of frequency. Two DSP I/O pins: DSP0, DSP1 are

provided for application.

PRELIMINARY

DS97TAD0100

Zilog

Z89175/Z89176

Voice Processing Controllers

PIN DESCRIPTION

Address

or I/O

(Nibble

P04

Programmable)

P05

P06

P07

P10

P11

P12

Address/Data

P13

or I/O

P14

(Byte

Programmable) P15

P16

P17

P20

P21

P22

I/O

P23

(Bit

Programmable) P24

P25

P26

P27

P00

P01

P02

P03

Port 0

Timer 0

Capture Reg.

Timer 1

256 x 8 Bit

Port 3

24 Kbytes

Program

ROM

(Z89175)

Internal Address Bus

Z8 Core

Internal Data Bus

Expanded

Port 4

P40

P41

P42

I/O

P43

(Bit

P44 Programmable)

P45

P46

P47

P31

P32

P33

Input

P34

P35 Output

P36

P37

Port 1

Expanded Register

File

(Z8)

Peripheral

(DSP)

mailbox

Port 2

Internal Address Bus

8K Words

Program

ROM

Internal Data Bus

INT 1

Extended Bus of the DSP

256 Word

RAM 0

256 Word

RAM 1

Port 5

DSP Core

P50

P51

P52

P53

P54

P55

P56

P57

I/O

(Bit

Programmable)

RMLS

/AS

/DS

R/W

XTAL1

XTAL2

VDD

GND

/RESET

INT 2

Ext.

Memory

Control

DSP Port

Extended Bus of the DSP

Timer 2

Timer 3

PWM

(10-Bit)

OSC

DSP0

DSP1

PWM

Power

ADC

(8-Bit)

AN IN

AN VDD

AN GND

VREF+

VREF-

OSC1

OSC2

32 kHz

OSC

Figure 1. Z89175/176 Functional Block Diagram

DS97TAD0100

PRELIMINARY

Z89175/Z89176

Voice Processing Controllers

Zilog

PIN DESCRIPTION

(Continued)

P06

P05

P04

P03

P02

P01

P00

GND

P17

P16

P15

P14

P13

P12

P11

P10

GND

AGND

VREF-

ANIN

P07

VCC

OSC02

OSC01

GND

VCC

P51

P50

P47

P46

P45

P44

P43

P42

P41

P40

P27

P26

P25

P24

P23

P22

100-Pin QFP

100

VREF+

ANVDD

GND

PWM

RMLS

DSP1

DSP0

/AS

/DS

R//W

P57

P56

P55

P54

VCC

XTAL2

XTAL1

P53

P52

P37

P36

P35

P34

P33

P32

P31

/RESET

P20

P21

Figure 2. Z89175 100-Pin QFP Pin Conﬁguration

PRELIMINARY

DS97TAD0100

Zilog

Table 1. Z89175 100-Pin QFP Pin Identiﬁcation

I/O Port

Symbol

GND

VREF+

ANV

PWM

RMLS

DSP1-0

/AS

/DS

R//W

P57-P54

XTAL2

XTAL1

P53-P52

P37-P34

P33-P31

/RESET

P20-P27

P40-P47

P50-P51

OSC1

OSC2

P07-P00

P17-P10

ANGND

VREF-

ANIN

Number

3, 53, 88, 97

16, 47, 77

6, 7

12-15

19, 20

21-24

25-27

29-36

37-44

45, 46

48-52

56-76

78, 79

80-87

89-96

100

Input/Output

Output

Input

Output

Input/Output

Output

Input

Input/Output

Output

Input

Input/Output

Input

Output

Direction

Digital Ground

Digital V

= +5V

Z89175/Z89176

Voice Processing Controllers

Function

Analog Voltage Ref+

Analog V

PWM Output

Control Input

DSP User Output 1, 0

Address Strobe

Data Strobe

Read/Write

No Connection

Port 5 Bit 7-4

Crystal Output (20.48 or 29.49 MHz)

Crystal Input (20.48 or 29.49 MHz)

Port 5 Bit 3-2

Port 3 Bit 7-4

Port 3 Bit 3-1

Reset

Port 2, Bit 0-7

Port 4, Bit 0-7

Port 5, Bit 0-1

No Connection

Crystal Input (32.768 kHz)

Crystal Output (32.768 kHz)

No Connection

Port 0, Bit 7-0

Port 1, Bit 7-0

Analog GND

Analog Voltage Ref-

Analog Input

Input/Output

Input

DS97TAD0100

PRELIMINARY

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Z8917520FSC Related Products

	Z8917520FSC	Z8917529ASC	Z8917629FSC
Description	IC 8-BIT, 20.48 MHz, MIXED DSP, PQFP100, QFP-100, Digital Signal Processor	Mixed Signal Processor, 8-Bit Size, 8-Ext Bit, 29.49MHz, CMOS, PQFP100, VQFP-100	Mixed Signal Processor, 8-Bit Size, 8-Ext Bit, 29.49MHz, CMOS, PQFP100, QFP-100
Is it Rohs certified?	incompatible	incompatible	incompatible
Maker	Zilog, Inc.	Zilog, Inc.	Zilog, Inc.
Parts packaging code	QFP	QFP	QFP
package instruction	QFP, QFP100,.7X.9	VQFP-100	QFP-100
Contacts	100	100	100
Reach Compliance Code	unknown	unknow	unknow
Address bus width	16	16	16
barrel shifter	YES	YES	YES
bit size	8	8	8
boundary scan	NO	NO	NO
CPU series	Z8	Z8	Z8
maximum clock frequency	20.48 MHz	29.49 MHz	29.49 MHz
External data bus width	8	8	8
Format	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	R-PQFP-G100	S-PQFP-G100	R-PQFP-G100
JESD-609 code	e0	e0	e0
length	20 mm	14 mm	20 mm
low power mode	YES	YES	YES
Number of terminals	100	100	100
Maximum operating temperature	70 °C	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QFP	LFQFP	QFP
Encapsulate equivalent code	QFP100,.7X.9	QFP100,.63SQ,20	QFP100,.7X.9
Package shape	RECTANGULAR	SQUARE	RECTANGULAR
Package form	FLATPACK	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK
Peak Reflow Temperature (Celsius)	225	240	240
power supply	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified
RAM (bytes)	256	256	256
rom(word)	24576	24576	-
Maximum seat height	3.1 mm	1.6 mm	3.1 mm
speed	20.4 MHz	29.4 MHz	29.4 MHz
Maximum slew rate	65 mA	65 mA	65 mA
Maximum supply voltage	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.5 mm	0.65 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	14 mm	14 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, MIXED	DIGITAL SIGNAL PROCESSOR, MIXED	DIGITAL SIGNAL PROCESSOR, MIXED
ROM programmability	MROM	MROM	-
ECCN code	-	3A991.A.2	3A991.A.2

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