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MC100EPT21
3.3V Differential
LVPECL/LVDS/CML to
LVTTL/LVCMOS Translator
The MC100EPT21 is a Differential LVPECL/LVDS/CML to
LVTTL/LVCMOS translator. Because LVPECL (Positive ECL),
LVDS, and positive CML input levels and LVTTL/LVCMOS output
levels are used, only +3.3 V and ground are required. The small
outline 8−lead SOIC package makes the EPT21 ideal for applications
which require the translation of a clock or data signal.
The V
BB
output allows this EPT21 to be cap coupled in either
single−ended or differential input mode. When single−ended cap
coupled, V
BB
output is tied to the D input and D is driven for a
non−inverting buffer, or V
BB
output is tied to the D input and D is
driven for an inverting buffer. When cap coupled differentially, V
BB
output is connected through a resistor to each input pin. If used, the
V
BB
pin should be bypassed to V
CC
via a 0.01
mF
capacitor. For
additional information see AND8020/D. For a single−ended direct
connection use an external voltage reference source such as a resistor
divider. Do not use V
BB
for a single−ended direct connection or port to
another device.
Features
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MARKING
DIAGRAMS*
8
8
1
SO−8
D SUFFIX
CASE 751
1
8
8
1
TSSOP−8
DT SUFFIX
CASE 948R
1
KA21
ALYWG
G
KPT21
ALYW
G
•
•
•
•
•
•
•
•
1.4 ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
24 mA TTL outputs
Operating Range: V
CC
= 3.0 V to 3.6 V with GND = 0 V
The 100 Series Contains Temperature Compensation
V
BB
Output
Pb−Free Packages are Available
A
L
Y
W
M
G
DFN8
MN SUFFIX
CASE 506AA
1
3RMG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
March, 2010
−
Rev. 21
1
Publication Order Number:
MC100EPT21/D
MC100EPT21
Table 1. PIN DESCRIPTION
NC
1
8
V
CC
Q
D
2
LVTTL
7
Q
D*, D*
V
CC
V
BB
D
3
LVPECL
6
NC
GND
NC
EP
V
BB
4
5
GND
PIN
FUNCTION
LVTTL/LVCMOS Output
Differential LVPECL/LVDS/CML Input
Positive Supply
Output Reference Voltage
Ground
No Connect
(DFN8 only) Thermal exposed pad must be
connected to a sufficient thermal conduit. Elec-
trically connect to the most negative supply
(GND) or leave unconnected, floating open.
Figure 1. Logic Diagram and 8−Lead Pinout
(Top View)
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
* Pin will default to 1/2 of V
CC
when left open.
Value
D
D
D, D
Human Body Model
Machine Model
Charged Device Model
50 kW
50 kW
50 kW
> 1.5 kV
> 100 V
> 2 kV
Level 1
UL 94 V−0 @ 0.125 in
81 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
IN
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
q
JA
T
sol
q
JC
Parameter
PECL Power Supply
PECL Input Voltage
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
< 2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
(Note 2)
DFN8
SO−8
SO−8
SO−8
TSSOP−8
TSSOP−8
TSSOP−8
DFN8
DFN8
Condition 1
GND = 0 V
GND = 0 V
V
I
V
CC
Condition 2
Rating
3.8
0 to 3.8
±
0.5
−40
to +85
−65
to +150
190
130
41 to 44
185
140
41 to 44
129
84
265
265
35 to 40
Unit
V
V
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
°C/W
Thermal Resistance (Junction−to−Case)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power)
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2
MC100EPT21
Table 4. PECL INPUT DC CHARACTERISTICS
V
CC
= 3.3 V, GND = 0.0 V (Note 3)
−40°C
Symbol
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
Input HIGH Current
Input LOW Current
−150
Min
2075
1355
1775
1.2
1875
Typ
Max
2420
1675
1975
3.3
Min
2075
1355
1775
1.2
1875
25°C
Typ
Max
2420
1675
1975
3.3
Min
2075
1355
1775
1.2
1875
85°C
Typ
Max
2420
1675
1975
3.3
Unit
mV
mV
mV
V
I
IH
I
IL
150
−150
150
−150
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input parameters vary 1:1 with V
CC
.
4. V
IHCMR
min varies 1:1 with GND, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the
differential input signal.
Table 5. LVTTL/LVCMOS OUTPUT DC CHARACTERISTICS
V
CC
= 3.3 V, GND = 0.0 V, T
A
=
−40°C
to 85°C
Symbol
V
OH
V
OL
I
CCH
I
CCL
I
OS
Characteristic
Output HIGH Voltage
Output LOW Voltage
Power Supply Current
Power Supply Current
Output Short Circuit Current
Condition
I
OH
=
−3.0
mA
I
OL
= 24 mA
Outputs set to HIGH
Outputs set to LOW
5
8
−130
17
21
Min
2.4
0.5
25
30
−80
Typ
Max
Unit
V
V
mA
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0.0 V (Note 5)
−40°C
Symbol
f
max
t
PLH
,
t
PHL
t
SKEW
t
SKPP
t
JITTER
V
PP
t
r
t
f
Characteristic
Maximum Frequency
(Figure 2)
Propagation Delay to
Output Differential
Duty Cycle Skew (Note 6)
Part−to−Part Skew (Note 6)
Random Clock Jitter (RMS)
Input Voltage Swing
(Differential Configuration)
Output Rise/Fall Times
(0.8V
−
2.0V)
Q, Q
150
3.5
800
Min
275
800
1200
45
Typ
350
1400
1400
50
2050
1800
55
500
5
1200
150
3.5
800
Max
Min
275
800
1200
45
25°C
Typ
350
1400
1400
50
2250
1800
55
500
5
1200
150
3.5
800
Max
Min
275
900
1100
45
85°C
Typ
350
1600
1300
50
2950
1900
55
500
5
1200
Max
Unit
MHz
ps
%
ps
ps
mV
ps
250
600
900
250
600
900
250
600
900
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measured with a 750 mV 50% duty−cycle clock source. R
L
= 500
W
to GND and C
L
= 20 pF to GND. Refer to FIgure 3.
6. Skews are measured between outputs under identical transitions. Duty cycle skew is measured between differential outputs using the
deviations of the sum Tpw− and Tpw+.
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3
MC100EPT21
3000
V
OH
2500
V
OUTpp
(mV)
2000
V
OL
0.5 V
1500
1000
500
0
0
50
100
150
200
250
300
350
400
450
500
550
600
FREQUENCY (MHz)
Figure 2. F
max
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*C
L
includes
fixture
capacitance
C
L
*
R
L
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used For Device Evaluation
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