V58C2128(804/404/164)SAT
HIGH PERFORMANCE
2.5 VOLT 128 Mbit DDR SDRAM
4 BANKS X 4Mbit X 8 (804)
4 BANKS X 2Mbit X 16 (164)
4 BANKS X 8Mbit X 4 (404)
6
DDR332
7
DDR266A
7.5 ns
7 ns
143 MHz
75
PRELIMINARY
s
High speed data transfer rates with system
frequency up to 166 MHz
s
Data Mask for Write Control
s
Four Banks controlled by BA0 & BA1
s
Programmable CAS Latency: 2, 2.5
s
Programmable Wrap Sequence: Sequential
or Interleave
s
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
s
Automatic and Controlled Precharge Command
s
Power Down Mode
s
Auto Refresh and Self Refresh
s
Refresh Interval: 4096 cycles/64 ms
s
Available in 66-pin 400 mil TSOP
s
SSTL-2 Compatible I/Os
s
Double Data Rate (DDR)
s
Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
s
On-Chip DLL aligns DQ and DQs transitions with
CK transitions
s
Differential clock inputs CK and CK
s
Power Supply 2.5V ± 0.2V
s
QFC options for FET control. x4 parts.
*Note: DDR 266A Supports PC2100 module with 2-2-2 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
CILETIV LESOM
Clock Cycle Time (t
CK2
)
Clock Cycle Time (t
CK2.5
)
System Frequency (f
CK max
)
8
DDR200
10 ns
8 ns
125 MHz
DDR266B
10 ns
7.5 ns
133 MHz
6.5 ns
6 ns
166 MHz
Features
Description
The V58C2128(804/404/164)SAT is a four bank
DDR DRAM organized as 4 banks x 4Mbit x 8 (804),
4 banks x 2Mbit x 16 (404), or 4 banks x 8Mbit x 4
(164). The V58C2128(804/404/164)SAT achieves
high speed data transfer rates by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
Package Outline
JEDEC 66 TSOP II
•
CK Cycle Time (ns)
-6
•
Power
-8
•
-7
•
-75
•
Std.
•
L
•
Temperature
Mark
Blank
V58C2128(804/404/164)SAT Rev. 1.3 January 2002
1
V58C2128(804/404/164)SAT
66 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
8Mb x 16
16Mb x 8
32Mb x 4
Pin Names
CK, CK
CKE
CS
RAS
CAS
WE
DQS (UDQS, LDQS)
A
0
–A
11
BA0, BA1
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
Bank Select
DQ’s
DM (UDM, LDM)
V
DD
V
SS
V
DDQ
V
SSQ
NC
VREF
QFC
Data Input/Output
Data Mask
Power (+2.5V)
Ground
Power for I/O’s (+2.5V)
Ground for I/O’s
Not connected
Reference Voltage for Inputs
FET Control
CILETIV LESOM
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
V
DD
DQ
0
V
DDQ
NC
DQ
1
V
SSQ
NC
DQ
2
V
DDQ
NC
DQ
3
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
V58C2128(804/404/164)SAT Rev. 1.3 January 2002
V
DD
NC
V
DDQ
NC
DQ
0
V
SSQ
NC
NC
V
DDQ
NC
DQ
1
V
SSQ
NC
NC
V
DDQ
NC
NC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
66
65
64
63
62
61
60
59
58
57
56
V
SS
NC
V
SSQ
NC
DQ
3
V
DDQ
NC
NC
V
SSQ
NC
DQ
2
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
7
V
SSQ
NC
DQ
5
V
DDQ
NC
DQ
5
V
SSQ
NC
DQ
4
V
DDQ
NC
NC
V
SSQ
DQS
NC
V
REF
V
SS
DM
CK
CK
CKE
NC
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
QFC/NC QFC/NC QFC/NC
NC
NC
NC
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
55
66 PIN TSOP (II)
54
13
(400mil x 875 mil)
14
53
15
Bank Address
52
BA0-BA1
51
16
50
17
Row Address
49
18
A0-A11
19
48
20
Auto Precharge
47
A10
46
21
22
23
24
25
26
27
28
29
30
31
32
33
45
44
43
42
41
40
39
38
37
36
35
34
2
V58C2128(804/404/164)SAT
Column decoder
Sense amplifier & I(O) bus
Bank 0
Column decoder
Sense amplifier & I(O) bus
Bank 1
Column decoder
Sense amplifier & I(O) bus
Bank 2
Column decoder
Sense amplifier & I(O) bus
CKE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DQS
V58C2128(804/404/164)SAT Rev. 1.3 January 2002
3
QFC
CAS
RAS
WE
DM
CK
CK
CS
CILETIV LESOM
V
MOSEL VITELIC
MANUFACTURED
DDRSDRAM
CMOS
2.5V
128Mb, 4K Refresh
x8, x4, x16
4 Banks
SSTL
58
C
2 128(80/40/16) 4
S
A
T XX
SPEED
6 (166MHZ@CL2.5)
7 (143MHZ@CL2.5))
75(133MHZ@CL2.5)
8 (125MHZ@CL2.5)
COMPONENT
PACKAGE, T = TSOP
COMPONENT
REV LEVEL
Block Diagram
Column Addresses
32M x 4
Row Addresses
A0 - A11, BA0, BA1
A0 - A9, A11, AP, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Row decoder
Memory array
Bank 3
4096 x 1024
x8
4096 x 1024
x8
4096 x 1024
x8
4096 x 1024
x8
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
3
V58C2128(804/404/164)SAT
Block Diagram
Column Addresses
Column decoder
Sense amplifier & I(O) bus
Bank 0
Column decoder
Sense amplifier & I(O) bus
Bank 1
Column decoder
Sense amplifier & I(O) bus
Bank 2
Column decoder
Sense amplifier & I(O) bus
CKE
RAS
CK, CK
DLL
Strobe
Gen.
Data Strobe
DQS
V58C2128(804/404/164)SAT Rev. 1.3 January 2002
4
QFC
CAS
WE
DM
CK
CK
CS
CILETIV LESOM
16M x 8
A0 - A9, AP, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Row decoder
Memory array
Row decoder
Memory array
4096 x 512
x 16 bit
4096 x 512
x 16 bit
Input buffer
Output buffer
DQ
0
-DQ
7
Row Addresses
A0 - A11, BA0, BA1
Refresh Counter
Row decoder
Memory array
Row decoder
Memory array
Bank 3
4096 x 512
x 16 bit
4096 x 512
x 16 bit
Control logic & timing generator
V58C2128(804/404/164)SAT
Block Diagram
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Bank 0
Bank 1
Bank 2
Column decoder
Sense amplifier & I(O) bus
CKE
CK, CK
DLL
Strobe
Gen.
Data Strobe
DQS
Capacitance*
T
A
= 0 to 70°C, V
CC
= 2.5V
±
0.2V, f = 1 Mhz
Input Capacitance
BA0, BA1, CKE, CS, RAS, (CAS,
A0-A11, WE)
Input Capacitance (CK, CK)
Data & DQS I/O Capacitance
Input Capacitance (DM)
Symbol
Min
C
INI
C
IN2
C
OUT
C
IN3
2
2
4
4
Absolute Maximum Ratings*
Max Unit
3.0
3.0
5
5.0
pF
pF
pF
pF
*Note: Capacitance is sampled and not 100% tested.
Operating temperature range ..................0 to 70 °C
Storage temperature range ................-55 to 150 °C
V
DD
Supply Voltage Relative to V
SS
.....-1V to +3.6V
V
DDQ
Supply Voltage Relative to V
SS
......................................................-1V to +3.6V
VREF and Inputs Voltage Relative to V
SS
......................................................-1V to +3.6V
I/O Pins Voltage Relative to V
SS
.......................................... -0.5V to V
DDQ
+0.5V
Power dissipation .......................................... 1.6 W
Data out current (short circuit) ...................... 50 mA
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
V58C2128(804/404/164)SAT Rev. 1.3 January 2002
5
QFC
RAS
CAS
WE
DM
CK
CK
CS
CILETIV LESOM
8M x 16
Column Addresses
A0 - A8, AP, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Row decoder
Memory array
Row decoder
Memory array
4096 x 256
x 32 bit
4096 x 256
x 32 bit
Input buffer
Output buffer
DQ
0
-DQ
15
Row Addresses
A0 - A11, BA0, BA1
Refresh Counter
Row decoder
Memory array
Row decoder
Memory array
Bank 3
4096 x 256
x 32 bit
4096 x 256
x 32 bit
Control logic & timing generator
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