LF80538NE0251M datasheet, PDF - EEWORLD Datasheet

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LF80538NE0251M: DescriptionMicroprocessor, 1600MHz, CMOS, CPGA478, MICRO, FCPGA-478; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，71 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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LF80538NE0251M Overview

Microprocessor, 1600MHz, CMOS, CPGA478, MICRO, FCPGA-478

LF80538NE0251M Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Intel
Parts packaging code	PGA
package instruction	SPGA,
Contacts	478
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	32
boundary scan	YES
maximum clock frequency	533 MHz
External data bus width	64
Format	FIXED POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P478
length	35 mm
low power mode	YES
Number of terminals	478
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA
Package shape	SQUARE
Package form	GRID ARRAY, SHRINK PITCH
Certification status	Not Qualified
Maximum seat height	2.813 mm
speed	1600 MHz
Maximum supply voltage	1.3 V
Minimum supply voltage	1 V
Nominal supply voltage	1.2 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	1.27 mm
Terminal location	PERPENDICULAR
width	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Intel® Celeron® M Processor

on 65 nm Process

Datasheet

September 2006

Document Number: 312726-002

Contents

Introduction

.............................................................................................................. 7

1.1

Terminology ....................................................................................................... 8

1.2

References ......................................................................................................... 9

Low Power Features

................................................................................................ 11

2.1

Clock Control and Low Power States .................................................................... 11

2.1.1 Core Low-Power States ........................................................................... 12

2.1.2 Package Low Power States ...................................................................... 13

2.2

FSB Low Power Enhancements ............................................................................ 15

2.3

Processor Power Status Indicator (PSI#) Signal..................................................... 16

Electrical Specifications

........................................................................................... 17

3.1

FSB (Front Side Bus) and GTLREF........................................................................ 17

3.2

Power and Ground Pins ...................................................................................... 17

3.3

Decoupling Guidelines ........................................................................................ 17

3.3.1 VCC Decoupling...................................................................................... 18

3.3.2 FSB AGTL+ Decoupling ........................................................................... 18

3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking ........................................... 18

3.4

Voltage Identification and Power Sequencing ........................................................ 18

3.5

Catastrophic Thermal Protection .......................................................................... 22

3.6

Signal Terminations and Unused Pins ................................................................... 22

3.7

FSB Frequency Select Signals (BSEL[2:0])............................................................ 23

3.8

FSB Signal Groups............................................................................................. 23

3.9

CMOS Signals ................................................................................................... 25

3.10 Maximum Ratings.............................................................................................. 25

3.11 Processor DC Specifications ................................................................................ 25

Package Mechanical Specifications and Pin Information

.......................................... 31

4.1

Package Mechanical Specifications ....................................................................... 31

4.1.1 Package Mechanical Drawings .................................................................. 31

4.1.2 Processor Component Keep-Out Zones ...................................................... 35

4.1.3 Package Loading Specifications ................................................................ 35

4.1.4 Processor Mass Specifications .................................................................. 35

4.2

Processor Pinout and Pin List .............................................................................. 36

4.3

Alphabetical Signals Reference ............................................................................ 55

Thermal Specifications and Design Considerations

.................................................. 67

5.1

Thermal Specifications ....................................................................................... 69

5.1.1 Thermal Diode ....................................................................................... 69

5.1.2 Thermal Diode Offset .............................................................................. 72

5.1.3 Intel® Thermal Monitor........................................................................... 72

5.1.4 Digital Thermal Sensor............................................................................ 74

5.1.5 Out of Specification Detection .................................................................. 74

5.1.6 PROCHOT# Signal Pin ............................................................................. 74

Datasheet

Figures

Package-Level Low Power States ................................................................................11

Core Low Power States..............................................................................................12

Active VCC and ICC Load Line for the Celeron M Processor Standard Voltage ....................28

Active VCC and ICC Load Line for the Celeron M Processor Ultra Low Voltage....................28

Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ................................................32

Micro-FCPGA Processor Package Drawing (Sheet 2 of 2) ................................................33

Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ................................................34

Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ................................................35

Coordination of Core-Level Low Power States at the Package Level for the

Celeron M Processor .................................................................................................11

Voltage Identification Definition ..................................................................................19

BSEL[2:0] Encoding for BCLK Frequency......................................................................23

FSB Pin Groups ........................................................................................................24

Processor DC Absolute Maximum Ratings.....................................................................25

Voltage and Current Specifications for the Celeron M Processor Standard Voltage..............26

Voltage and Current Specifications for the Celeron M Processor Ultra Low Voltage .............27

FSB Differential BCLK Specifications ............................................................................29

AGTL+ Signal Group DC Specifications ........................................................................29

CMOS Signal Group DC Specifications..........................................................................30

Open Drain Signal Group DC Specifications ..................................................................30

The Coordinates of the Processor Pins As Viewed from the Top of the Package ..................36

Pin Listing by Pin Name .............................................................................................39

Pin Listing by Pin Number ..........................................................................................46

Signal Description.....................................................................................................55

Power Specifications for the Celeron M Processor Standard Voltage .................................68

Power Specifications for the Celeron M Processor Ultra Low Voltage.................................69

Thermal Diode Interface ............................................................................................70

Thermal Diode Parameters using Diode Model ..............................................................70

Thermal Diode Parameters using Transistor Mode .........................................................71

Thermal Diode n

trim

and Diode Correction Toffset..........................................................72

Tables

Datasheet

LF80538NE0251M Related Products

	LF80538NE0251M	LF80538NE0201M	BX80538410	BX80538430	LF80538NE0301M	BX80538420
Description	Microprocessor, 1600MHz, CMOS, CPGA478, MICRO, FCPGA-478	Microprocessor, 1460MHz, CMOS, CPGA478, MICRO, FCPGA-478	Microprocessor, 64-Bit, 1460MHz, CMOS, CPGA478, MICRO, FCPGA-478	Microprocessor, 1730MHz, CMOS, CPGA478, MICRO, FCPGA-478	Microprocessor, 64-Bit, 1730MHz, CMOS, CPGA478, MICRO, FCPGA-478	Microprocessor, 1600MHz, CMOS, CPGA478, MICRO, FCPGA-478
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Intel	Intel	Intel	Intel	Intel	Intel
Parts packaging code	PGA	PGA	PGA	PGA	PGA	PGA
package instruction	SPGA,	SPGA,	SPGA, PGA478,26X26,50	SPGA,	SPGA, PGA478,26X26,50	SPGA,
Contacts	478	478	478	478	478	478
Reach Compliance Code	unknown	unknown	compliant	unknown	compliant	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES
maximum clock frequency	533 MHz	533 MHz	533 MHz	533 MHz	533 MHz	533 MHz
External data bus width	64	64	64	64	64	64
Format	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT	FIXED POINT
Integrated cache	YES	YES	YES	YES	YES	YES
JESD-30 code	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478	S-CPGA-P478
length	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm
low power mode	YES	YES	YES	YES	YES	YES
Number of terminals	478	478	478	478	478	478
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	SPGA	SPGA	SPGA	SPGA	SPGA	SPGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH	GRID ARRAY, SHRINK PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.813 mm	8.813 mm	2.813 mm	2.813 mm	2.813 mm	2.813 mm
speed	1600 MHz	1460 MHz	1460 MHz	1730 MHz	1730 MHz	1600 MHz
Maximum supply voltage	1.3 V	1.3 V	1.3 V	1.3 V	1.3 V	1.3 V
Minimum supply voltage	1 V	1 V	1 V	1 V	1 V	1 V
Nominal supply voltage	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
surface mount	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
width	35 mm	35 mm	35 mm	35 mm	35 mm	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR

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