Numonyx™ StrataFlash
®
Embedded Memory
(J3-65nm)
256-Mbit
Datasheet
Product Features
Architecture
— Multi-Level Cell Technology: Highest
Density at Lowest Cost
— 256 symmetrically-sized blocks of 128
Kbytes
Performance
— 95 ns initial access time for Easy BGA
— 105 ns initial accsss time for TSOP
— 25 ns 16-word Asynchronous page-mode
reads
— 512-Word Buffer Programming at
1.46MByte/s (Typ)
Voltage and Power
— V
CC
(Core) = 2.7 V to 3.6 V
— V
CCQ
(I/O) = 2.7 V to 3.6 V
— Standby Current: 65 µA (Typ)
— Erase & Program Current: 35 mA (Typ)
— Page Read: 12 mA (Typ)
Quality and Reliability
— Operating temperature:
-40 °C to +85 °C
— 100K Minimum erase cycles per block
— 65 nm Numonyx
TM
ETOX™ X Process
technology
Security
— Enhanced security options for code
protection
— Absolute protection with V
PEN
= GND
— Individual block locking
— Block erase/program lockout during power
transition
— Password Access feature
— One-Time Programmable Register:
64 OTP bits, programmed with unique
information by Numonyx
64 OTP bits, available for customer
programming
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Numonyx™ Flash Data Integrator (FDI)
— Common Flash Interface (CFI) Compatible
Packaging
— 56-Lead TSOP
— 64-Ball Easy BGA package
319942-02
December 2008
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the
Numonyx website at
http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2008, Numonyx B.V., All Rights Reserved.
Datasheet
2
December 2008
319942-02
Numonyx™ StrataFlash
®
Embedded Memory (J3-65nm)
Contents
1.0
Functional Overview
.................................................................................................. 5
1.1
Document purpose .............................................................................................. 5
1.2
Product overview................................................................................................. 5
1.3
Configuration & Memory Map ................................................................................ 7
1.4
Device ID ........................................................................................................... 8
Package Information
................................................................................................. 9
2.1
56-Lead TSOP Package, 256-Mbit .......................................................................... 9
2.2
Easy BGA Package, 256-Mbit .............................................................................. 11
Ballout.....................................................................................................................
12
3.1
Easy BGA Ballout, 256-Mbit ................................................................................ 12
3.2
56-Lead TSOP Package Pinout, 256-Mbit .............................................................. 13
Signal Descriptions
.................................................................................................. 14
Bus Interface...........................................................................................................
15
5.1
Reads .............................................................................................................. 16
5.2
Writes.............................................................................................................. 16
5.3
Output Disable .................................................................................................. 16
5.4
Standby ........................................................................................................... 16
5.5
Reset............................................................................................................... 17
Command Set
.......................................................................................................... 18
6.1
Device Command Codes ..................................................................................... 18
6.2
Device Command Bus Cycle................................................................................ 19
Read
7.1
7.2
7.3
7.4
7.5
operation
........................................................................................................ 21
Read Array ....................................................................................................... 21
Asynchronous Page Mode Read ........................................................................... 21
Read Status Register ......................................................................................... 22
Read Device Information .................................................................................... 22
CFI Query ........................................................................................................ 22
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Program operation
.................................................................................................. 24
8.1
Single-Word/Byte Programming .......................................................................... 24
8.2
Buffered Programming ....................................................................................... 24
8.3
Suspend/Resume .............................................................................................. 25
Erase Operation.......................................................................................................
26
9.1
Block Erase ...................................................................................................... 26
9.2
Suspend/Resume .............................................................................................. 26
9.0
10.0 Security
................................................................................................................... 28
10.1 Normal Block Locking......................................................................................... 28
10.2 Configurable Block Locking ................................................................................. 28
10.3 VPEN Protection ................................................................................................ 29
10.4 Password Access ............................................................................................... 29
11.0 Registers
................................................................................................................. 30
11.1 Status Register ................................................................................................. 30
11.2 Status Signal .................................................................................................... 31
11.3 OTP Protection Register...................................................................................... 32
12.0 Power and Reset Specifications
............................................................................... 35
12.1 Power-Up and Power-Down................................................................................. 35
December 2008
319942-02
Datasheet
3
Numonyx™ StrataFlash
®
Embedded Memory (J3-65nm)
12.2
12.3
Reset Specifications ...........................................................................................36
Power Supply Decoupling....................................................................................37
13.0 Maximum Ratings and Operating Conditions
............................................................38
13.1 Absolute Maximum Ratings .................................................................................38
13.2 Operating Conditions..........................................................................................38
14.0 Electrical characteristics
..........................................................................................39
14.1 DC Current Specifications ...................................................................................39
14.2 DC Voltage Specifications....................................................................................40
14.3 Capacitance .....................................................................................................40
15.0 AC characteristics
....................................................................................................41
15.1 AC Test Conditions.............................................................................................41
15.2 AC Read Specifications .......................................................................................43
15.3 AC Write Specification ........................................................................................46
16.0 Program and erase characteristics
...........................................................................48
16.1 Program & Erase Specifications............................................................................48
17.0 Ordering Information...............................................................................................49
A
Reference Information
.............................................................................................50
A.1
Common Flash Interface .....................................................................................50
A.2
Query Structure Output ......................................................................................50
A.3
Flow Charts.......................................................................................................57
Terms, definitions, and acronyms
............................................................................62
B.1
Nomenclature....................................................................................................62
B.2
Acronyms .........................................................................................................62
B.3
Conventions......................................................................................................63
Revision History.......................................................................................................64
B
C
Datasheet
4
December 2008
319942-02
Numonyx™ StrataFlash
®
Embedded Memory (J3-65nm)
1.0
Functional Overview
The Numonyx™ StrataFlash
®
Embedded Memory (J3-65nm) provides improved
mainstream performance with enhanced security features, taking advantage of the
high quality and reliability of the NOR-based
Numonyx
65 nm ETOX™ X process technology.
Offered in 32-Mbit up through 256-Mbit densities, the Numonyx™ Embedded Memory
(J3-65nm) device brings reliable, low-voltage capability (3 V read, program, and
erase) with high speed, low-power operation. The Numonyx™ StrataFlash
®
Embedded
Memory (J3-65nm) device is ideal for code and data applications where high density
and low cost are required, such as in networking, telecommunications, digital set top
boxes, audio recording, and digital imaging. Numonyx Flash Memory components also
deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and Scalable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Numonyx
Flash Memory devices.
1.1
Document purpose
This document contains information pertaining to the Numonyx™ StrataFlash
®
Embedded Memory (J3-65nm) device features, operation, and specifications.
The Numonyx™ Embedded Memory (J3-65nm) device is offered in Single Bit Cell
technology for 32-, 64-, 128-Mbit densities. The Numonyx™ StrataFlash
®
Embedded
Memory (J3-65nm) device is offered in Multi-Level Cell technology for 256-Mbit density.
This document just covers 256-Mbit die information.
Unless otherwise indicated throughout the rest of this document, Numonyx™
StrataFlash
®
Embedded Memory (J3-65nm) is referred to as J3-65nm.
1.2
Product overview
The 256-Mbit J3-65nm is organized as 256 individual 128Kbyte symmetrical blocks.
A 128-bit Protection Register has multiple uses, including unique flash device
identification.
The J3-65nm device includes new security features that were not available on the
(previous) 0.25µm, 0.18µm, and 0.13µm versions of the J3 family. The new security
features can be implemented to protect critical code and data from unwanted
modification (program or erase). Usage can be defined to fit the specific needs of each
customer.
The J3-65nm optimized architecture and interface dramatically increases read
performance by supporting page-mode reads. This read mode is ideal for non-clock
memory systems.
The J3-65nm Common Flash Interface (CFI) permits software algorithms to be used for
entire families of devices. This allows device-independent, JEDEC ID-independent, and
forward- and backward-compatible software support for the specified flash device
families. Flash vendors can standardize their existing interfaces for long-term
compatibility.
The Scalable Command Set (SCS) allows a single, simple software driver in all host
systems to work with all SCS-compliant flash memory devices, independent of system-
level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally,
SCS provides the highest system/device data transfer rates and minimizes device and
system-level implementation costs.
December 2008
319942-02
Datasheet
5
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