HYI25DC256160CE-5 datasheet, PDF

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HYI25DC256160CE-5: DescriptionDDR DRAM, 16MX16, 0.5ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66; Categorystorage storage; File Size2MB，29 Pages; ManufacturerQIMONDA; Environmental Compliance

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HYI25DC256160CE-5 Overview

DDR DRAM, 16MX16, 0.5ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66

HYI25DC256160CE-5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	QIMONDA
Parts packaging code	TSOP2
package instruction	TSOP2, TSSOP66,.46
Contacts	66
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PDSO-G66
length	22.22 mm
memory density	268435456 bit
Memory IC Type	DDR DRAM
memory width	16
Humidity sensitivity level	1
Number of functions	1
Number of ports	1
Number of terminals	66
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSSOP66,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	2.6 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.5 V
Nominal supply voltage (Vsup)	2.6 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	10.16 mm

HYI25DC256160CE-5 Preview

September 2006

H Y I 25 D C256 16 0 C E

H Y I 25 D C256 80 0 C E

256 Mbit Double-Data-Rate SDRAM

DDR SDRAM

RoHS Compliant

Internet Data Sheet

Rev. 1.00

Internet Data Sheet

HYI25DC256[16/80]0CE

256 Mbit Double-Data-Rate SDRAM

Revision History: Rev. 1.00, 2006-09

All

Adapted internet edition

First data sheet

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_rev400 / 3.2 QAG / 2006-08-01

03292006-O26P-394X

Internet Data Sheet

HYI25DC256[16/80]0CE

256 Mbit Double-Data-Rate SDRAM

1.1

•

Overview

Features

This chapter lists all main features of the product family HYI25DC256[16/80]0CE and the ordering information.

Double data rate architecture: two data transfers per clock cycle

Industrial operating temperature range: -40°C to +85°C

Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver

DQS is edge-aligned with data for reads and is center-aligned with data for writes

Differential clock inputs (CK and CK)

Four internal banks for concurrent operation

Data mask (DM) for write data

DLL aligns DQ and DQS transitions with CK transitions

Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

Burst Lengths: 2, 4, or 8

CAS Latency: 2, 2.5, 3

Auto Precharge option for each burst access

Auto Refresh and Self Refresh Modes

RAS-lockout supported

RAP

RCD

7.8

µs

Maximum Average Periodic Refresh Interval

2.5 V (SSTL_2 compatible) I/O

DDQ

= 2.6 V

0.1 V

= 2.6 V

0.1 V

PG-TSOPII-66 package

Lead- and halogene-free = green product

TABLE 1

Performance

Part Number Speed Code

Speed Grade

Max. Clock Frequency

Component

@CL3

@CL2.5

@CL2

–5

DDR400B

–6

DDR333B

166

133

Unit

—

MHz

CK3

CK2.5

CK2

200

166

133

Rev. 1.00, 2006-09

03292006-O26P-394X

Internet Data Sheet

HYI25DC256[16/80]0CE

256 Mbit Double-Data-Rate SDRAM

1.2

Description

accesses to the DDR SDRAM are burst oriented; accesses

start at a selected location and continue for a programmed

number of locations in a programmed sequence. Accesses

begin with the registration of an Active command, which is

then followed by a Read or Write command. The address bits

registered coincident with the Active command are used to

select the bank and row to be accessed. The address bits

registered coincident with the Read or Write command are

used to select the bank and the starting column location for

the burst access.

The DDR SDRAM provides for programmable Read or Write

burst lengths of 2, 4 or 8 locations. An Auto Precharge

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst access. As

with standard SDRAMs, the pipelined, multibank architecture

of DDR SDRAMs allows for concurrent operation, thereby

providing high effective bandwidth by hiding row precharge

and activation time.

An auto refresh mode is provided along with a power-saving

power-down mode. All inputs are compatible with the Industry

Standard for SSTL_2. All outputs are SSTL_2, Class II

compatible.

Note: The functionality described and the timing

specifications included in this data sheet are for the

DLL Enabled mode of operation.

The 256 Mbit Double-Data-Rate SDRAM is a high-speed

CMOS, dynamic random-access memory containing

268,435,456 bits. It is internally configured as a quad-bank

DRAM.

The 256 Mbit Double-Data-Rate SDRAM uses a double-

data-rate architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n prefetch

architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write

access

for

the

256 Mbit Double-Data-Rate SDRAM

effectively consists of a single 2n-bit wide, one clock cycle

data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half-clock-cycle data transfers

at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during Reads and

by the memory controller during Writes. DQS is edge-aligned

with data for Reads and center-aligned with data for Writes.

The 256 Mbit Double-Data-Rate SDRAM operates from a

differential clock (CK and CK; the crossing of CK going HIGH

and CK going LOW is referred to as the positive edge of CK).

Commands (address and control signals) are registered at

every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both edges of

DQS, as well as to both edges of CK.Read and write

TABLE 2

Ordering Information for RoHS Compliant Products

Product Type

HYI25DC256800CE–5

HYI25DC256160CE–5

HYI25DC256800CE–6

HYI25DC256160CE–6

Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed

Latencies

(MHz) Latencies

(MHz)

×8

×16

×8

×16

2.5-3-3

166

2-3-3

133

DDR333B

3-3-3

200

2.5-3-3

166

DDR400B

Package

PG-TSOPII-66

Note

1)2)

1) HYI: designator for memory components

25D: DDR SDRAMs at

DDQ

= 2.5 V

256: 256-Mbit density

160/800: Product variations

×16

and

×8

C: Die revision CE: Package type TSOP (Lead & Halogene free)

2) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers..

Rev. 1.00, 2006-09

03292006-O26P-394X

Internet Data Sheet

HYI25DC256[16/80]0CE

256 Mbit Double-Data-Rate SDRAM

Pin Configuration

The pin configuration of a DDR SDRAM is listed by function in

Table 3

(60 pins). The abbreviations used in the Pin#/Buffer#

column are explained in

Table 4

and

Table 5

respectively.

TABLE 3

Pin Configuration of DDR SDRAM

Ball#/Pin#

Clock Signals

Control Signals

RAS

CAS

BA0

BA1

A10

A11

A12

SSTL

—

Address Signal 13

Note: 512 Mbit or smaller dies

Address Bus 11:0

Row Address Strobe

Column Address Strobe

Write Enable

Chip Select

Bank Address Bus 2:0

CKE

SSTL

Clock Signal

Complementary Clock Signal

Clock Enable

Name

Type

Buffer

Type

Function

Address Signals

Rev. 1.00, 2006-09

03292006-O26P-394X

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HYI25DC256160CE-5 Related Products

	HYI25DC256160CE-5	HYI25DC256800CE-6	HYI25DC256160CE-6	HYI25DC256800CE-5
Description	DDR DRAM, 16MX16, 0.5ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66	DDR DRAM, 32MX8, 0.7ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66	DDR DRAM, 16MX16, 0.7ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66	DDR DRAM, 32MX8, 0.5ns, CMOS, PDSO66, GREEN, PLASTIC, TSOP2-66
Is it Rohs certified?	conform to	conform to	conform to	conform to
Maker	QIMONDA	QIMONDA	QIMONDA	QIMONDA
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46	TSOP2, TSSOP66,.46
Contacts	66	66	66	66
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.5 ns	0.7 ns	0.7 ns	0.5 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz	166 MHz	166 MHz	200 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
interleaved burst length	2,4,8	2,4,8	2,4,8	2,4,8
JESD-30 code	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66
length	22.22 mm	22.22 mm	22.22 mm	22.22 mm
memory density	268435456 bit	268435456 bit	268435456 bit	268435456 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	8	16	8
Humidity sensitivity level	1	1	1	1
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	66	66	66	66
word count	16777216 words	33554432 words	16777216 words	33554432 words
character code	16000000	32000000	16000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
organize	16MX16	32MX8	16MX16	32MX8
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2	TSOP2
Encapsulate equivalent code	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46	TSSOP66,.46
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260	260
power supply	2.6 V	2.5 V	2.5 V	2.6 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES
Continuous burst length	2,4,8	2,4,8	2,4,8	2,4,8
Maximum slew rate	0.25 mA	0.215 mA	0.215 mA	0.25 mA
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.5 V	2.3 V	2.3 V	2.5 V
Nominal supply voltage (Vsup)	2.6 V	2.5 V	2.5 V	2.6 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	40	40	40	40
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm

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