September 2006
H Y I 25 D C256 16 0 C E
H Y I 25 D C256 80 0 C E
256 Mbit Double-Data-Rate SDRAM
DDR SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.00
Internet Data Sheet
HYI25DC256[16/80]0CE
256 Mbit Double-Data-Rate SDRAM
Revision History: Rev. 1.00, 2006-09
All
All
Adapted internet edition
First data sheet
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
03292006-O26P-394X
2
Internet Data Sheet
HYI25DC256[16/80]0CE
256 Mbit Double-Data-Rate SDRAM
1
1.1
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Overview
Features
This chapter lists all main features of the product family HYI25DC256[16/80]0CE and the ordering information.
Double data rate architecture: two data transfers per clock cycle
Industrial operating temperature range: -40°C to +85°C
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: 2, 2.5, 3
Auto Precharge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported
t
RAP
=
t
RCD
7.8
µs
Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
DDQ
= 2.6 V
±
0.1 V
V
DD
= 2.6 V
±
0.1 V
PG-TSOPII-66 package
Lead- and halogene-free = green product
TABLE 1
Performance
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Component
@CL3
@CL2.5
@CL2
–5
DDR400B
–6
DDR333B
166
166
133
Unit
—
MHz
MHz
MHz
f
CK3
f
CK2.5
f
CK2
200
166
133
Rev. 1.00, 2006-09
03292006-O26P-394X
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Internet Data Sheet
HYI25DC256[16/80]0CE
256 Mbit Double-Data-Rate SDRAM
1.2
Description
accesses to the DDR SDRAM are burst oriented; accesses
start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses
begin with the registration of an Active command, which is
then followed by a Read or Write command. The address bits
registered coincident with the Active command are used to
select the bank and row to be accessed. The address bits
registered coincident with the Read or Write command are
used to select the bank and the starting column location for
the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access. As
with standard SDRAMs, the pipelined, multibank architecture
of DDR SDRAMs allows for concurrent operation, thereby
providing high effective bandwidth by hiding row precharge
and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the Industry
Standard for SSTL_2. All outputs are SSTL_2, Class II
compatible.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The 256 Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-bank
DRAM.
The 256 Mbit Double-Data-Rate SDRAM uses a double-
data-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access
for
the
256 Mbit Double-Data-Rate SDRAM
effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads and
by the memory controller during Writes. DQS is edge-aligned
with data for Reads and center-aligned with data for Writes.
The 256 Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.Read and write
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
HYI25DC256800CE–5
HYI25DC256160CE–5
HYI25DC256800CE–6
HYI25DC256160CE–6
Org. CAS-RCD-RP Clock CAS-RCD-RP Clock Speed
Latencies
(MHz) Latencies
(MHz)
×8
×16
×8
×16
2.5-3-3
166
2-3-3
133
DDR333B
3-3-3
200
2.5-3-3
166
DDR400B
Package
PG-TSOPII-66
Note
1)2)
1) HYI: designator for memory components
25D: DDR SDRAMs at
V
DDQ
= 2.5 V
256: 256-Mbit density
160/800: Product variations
×16
and
×8
C: Die revision CE: Package type TSOP (Lead & Halogene free)
2) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers..
Rev. 1.00, 2006-09
03292006-O26P-394X
4
Internet Data Sheet
HYI25DC256[16/80]0CE
256 Mbit Double-Data-Rate SDRAM
2
Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in
Table 3
(60 pins). The abbreviations used in the Pin#/Buffer#
column are explained in
Table 4
and
Table 5
respectively.
TABLE 3
Pin Configuration of DDR SDRAM
Ball#/Pin#
Clock Signals
45
46
44
Control Signals
23
22
21
24
26
27
29
30
31
32
35
36
37
38
39
40
28
41
42
17
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
NC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
NC
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
Address Signal 13
Note: 512 Mbit or smaller dies
Address Bus 11:0
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Bank Address Bus 2:0
CK
CK
CKE
I
I
I
SSTL
SSTL
SSTL
Clock Signal
Complementary Clock Signal
Clock Enable
Name
Pin
Type
Buffer
Type
Function
Address Signals
Rev. 1.00, 2006-09
03292006-O26P-394X
5
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