LFXP10C-5FN388I datasheet, PDF

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LFXP10C-5FN388I: DescriptionField Programmable Gate Array, 1216 CLBs, CMOS, PBGA388, 23 X 23 MM, LEAD FREE, FPBGA-388; CategoryProgrammable logic devices Programmable logic; File Size7MB，386 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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LFXP10C-5FN388I Overview

Field Programmable Gate Array, 1216 CLBs, CMOS, PBGA388, 23 X 23 MM, LEAD FREE, FPBGA-388

LFXP10C-5FN388I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	BGA
package instruction	23 X 23 MM, LEAD FREE, FPBGA-388
Contacts	388
Reach Compliance Code	unknown
ECCN code	EAR99
JESD-30 code	S-PBGA-B388
JESD-609 code	e1
length	23 mm
Humidity sensitivity level	3
Configurable number of logic blocks	1216
Number of terminals	388
Maximum operating temperature	85 °C
Minimum operating temperature
organize	1216 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	250
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.6 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	23 mm

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LatticeXP Family Handbook

HB1001 Version 02.9, April 2007

LatticeXP Family Handbook

Table of Contents

April 2007

Section I. LatticeXP Family Data Sheet

Introduction

Features ............................................................................................................................................................. 1-1

Introduction ........................................................................................................................................................ 1-2

Architecture

Architecture Overview ........................................................................................................................................ 2-1

PFU and PFF Blocks................................................................................................................................. 2-2

Slice .......................................................................................................................................................... 2-3

Routing...................................................................................................................................................... 2-6

Clock Distribution Network ................................................................................................................................. 2-6

Primary Clock Sources.............................................................................................................................. 2-6

Secondary Clock Sources......................................................................................................................... 2-7

Clock Routing............................................................................................................................................ 2-8

sysCLOCK Phase Locked Loops (PLLs) .................................................................................................. 2-9

Dynamic Clock Select (DCS) ........................................................................................................................... 2-11

sysMEM Memory ............................................................................................................................................. 2-11

sysMEM Memory Block........................................................................................................................... 2-11

Bus Size Matching .................................................................................................................................. 2-12

RAM Initialization and ROM Operation ................................................................................................... 2-12

Memory Cascading ................................................................................................................................. 2-12

Single, Dual and Pseudo-Dual Port Modes............................................................................................. 2-12

Memory Core Reset ................................................................................................................................ 2-14

Programmable I/O Cells (PICs)........................................................................................................................ 2-15

PIO .......................................................................................................................................................... 2-16

DDR Memory Support...................................................................................................................................... 2-20

DLL Calibrated DQS Delay Block ........................................................................................................... 2-20

Polarity Control Logic .............................................................................................................................. 2-22

sysIO Buffer ..................................................................................................................................................... 2-22

Hot Socketing.......................................................................................................................................... 2-25

Sleep Mode ...................................................................................................................................................... 2-25

SLEEPN Pin Characteristics ................................................................................................................... 2-26

Configuration and Testing ................................................................................................................................ 2-26

IEEE 1149.1-Compliant Boundary Scan Testability................................................................................ 2-26

Device Configuration............................................................................................................................... 2-26

Internal Logic Analyzer Capability (ispTRACY)....................................................................................... 2-27

Oscillator ................................................................................................................................................. 2-27

Density Shifting ................................................................................................................................................ 2-28

DC and Switching Characteristics

Absolute Maximum Ratings ............................................................................................................................... 3-1

Recommended Operating Conditions ................................................................................................................ 3-1

Hot Socketing Specifications.............................................................................................................................. 3-2

DC Electrical Characteristics.............................................................................................................................. 3-3

Supply Current (Sleep Mode)............................................................................................................................. 3-3

Supply Current (Standby)................................................................................................................................... 3-4

Initialization Supply Current ............................................................................................................................... 3-5

Programming and Erase Flash Supply Current ................................................................................................. 3-6

sysIO Recommended Operating Conditions...................................................................................................... 3-7

sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-8

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

Lattice Semiconductor

Table of Contents

LatticeXP Family Handbook

sysIO Differential Electrical Characteristics ....................................................................................................... 3-9

LVDS......................................................................................................................................................... 3-9

Differential HSTL and SSTL............................................................................................................................. 3-10

LVDS25E ................................................................................................................................................ 3-10

BLVDS .................................................................................................................................................... 3-10

LVPECL .................................................................................................................................................. 3-12

RSDS ...................................................................................................................................................... 3-12

Typical Building Block Function Performance.................................................................................................. 3-14

Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ............................................................................... 3-14

Register to Register Performance........................................................................................................... 3-14

Derating Logic Timing ...................................................................................................................................... 3-15

LatticeXP External Switching Characteristics .................................................................................................. 3-16

LatticeXP Internal Timing Parameters ............................................................................................................. 3-18

Timing Diagrams .............................................................................................................................................. 3-20

PFU Timing Diagrams............................................................................................................................. 3-20

EBR Memory Timing Diagrams........................................................................................................................ 3-21

LatticeXP Family Timing Adders ...................................................................................................................... 3-23

sysCLOCK PLL Timing .................................................................................................................................... 3-25

LatticeXP sysCONFIG Port Timing Specifications........................................................................................... 3-26

Flash Download Time ...................................................................................................................................... 3-27

JTAG Port Timing Specifications ..................................................................................................................... 3-27

Switching Test Conditions................................................................................................................................ 3-28

Pinout Information

Signal Descriptions ............................................................................................................................................ 4-1

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-3

Pin Information Summary................................................................................................................................... 4-4

Power Supply and NC Connections................................................................................................................... 4-6

LFXP3 Logic Signal Connections: 100 TQFP .................................................................................................... 4-7

LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP................................................................................... 4-10

LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP .................................................................................. 4-14

LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA................................................................................ 4-19

LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA.............................................................................. 4-26

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA............................................................... 4-34

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA.............................................................................. 4-43

Ordering Information

Part Number Description.................................................................................................................................... 5-1

Ordering Information .......................................................................................................................................... 5-1

Conventional Packaging ........................................................................................................................... 5-2

Lead-free Packaging ................................................................................................................................. 5-8

Supplemental Information

For Further Information ...................................................................................................................................... 6-1

Revision History

Revision History ................................................................................................................................................. 7-1

Section II. LatticeXP Family Technical Notes

LatticeECP/EC and LatticeXP sysIO Usage Guide

Introduction ........................................................................................................................................................ 8-1

sysIO Buffer Overview ....................................................................................................................................... 8-1

Supported sysIO Standards ............................................................................................................................... 8-1

sysIO Banking Scheme...................................................................................................................................... 8-2

CCIO

(1.2V/1.5V/1.8V/2.5V/3.3V) ............................................................................................................ 8-3

CCAUX

(3.3V) ........................................................................................................................................... 8-3

CCJ

(1.2V/1.5V/1.8V/2.5V/3.3V).............................................................................................................. 8-3

Input Reference Voltage (V

REF1,

REF2

)................................................................................................... 8-3

REF1

for DDR Memory Interface ............................................................................................................. 8-3

Lattice Semiconductor

Table of Contents

LatticeXP Family Handbook

Mixed Voltage Support in a Bank.............................................................................................................. 8-4

sysIO Standards Supported in Each Bank......................................................................................................... 8-5

LVCMOS Buffer Configurations ......................................................................................................................... 8-5

Programmable Pull-up/Pull-Down/Buskeeper........................................................................................... 8-5

Programmable Drive ................................................................................................................................. 8-5

Programmable Slew Rate ......................................................................................................................... 8-7

Open Drain Control ................................................................................................................................... 8-7

Differential SSTL and HSTL Support ................................................................................................................. 8-7

PCI Support with Programmable PCICLAMP .................................................................................................... 8-7

5V Interface with PCI Clamp Diode.................................................................................................................... 8-8

Programmable Input Delay ................................................................................................................................ 8-9

Software sysIO Attributes................................................................................................................................... 8-9

IO_TYPE ................................................................................................................................................... 8-9

OPENDRAIN........................................................................................................................................... 8-10

DRIVE ..................................................................................................................................................... 8-10

PULLMODE ............................................................................................................................................ 8-11

PCICLAMP.............................................................................................................................................. 8-11

SLEWRATE ............................................................................................................................................ 8-11

FIXEDDELAY.......................................................................................................................................... 8-11

DIN/DOUT............................................................................................................................................... 8-11

LOC......................................................................................................................................................... 8-12

Design Considerations and Usage................................................................................................................... 8-12

Banking Rules ......................................................................................................................................... 8-12

Differential I/O Rules ............................................................................................................................... 8-12

Assigning V

REF

/ V

REF

Groups for Referenced Inputs............................................................................. 8-12

Differential I/O Implementation......................................................................................................................... 8-13

LVDS....................................................................................................................................................... 8-13

BLVDS .................................................................................................................................................... 8-13

RSDS ...................................................................................................................................................... 8-13

LVPECL .................................................................................................................................................. 8-13

Differential SSTL and HSTL.................................................................................................................... 8-13

Technical Support Assistance.......................................................................................................................... 8-13

Appendix A. HDL Attributes for Synplify

and Precision

RTL Synthesis ........................................................ 8-14

VHDL Synplify/Precision RTL Synthesis.......................................................................................................... 8-14

Syntax ..................................................................................................................................................... 8-14

Examples ................................................................................................................................................ 8-14

Verilog for Synplify ........................................................................................................................................... 8-17

Syntax ..................................................................................................................................................... 8-17

Examples ................................................................................................................................................ 8-17

Verilog for Precision RTL Synthesis................................................................................................................. 8-19

Syntax ..................................................................................................................................................... 8-19

Example .................................................................................................................................................. 8-19

Appendix B. sysIO Attributes Using Preference Editor User Interface............................................................. 8-21

Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-22

IOBUF ..................................................................................................................................................... 8-22

LOCATE.................................................................................................................................................. 8-22

USE DIN CELL........................................................................................................................................ 8-23

USE DOUT CELL.................................................................................................................................... 8-23

PGROUP VREF ...................................................................................................................................... 8-23

Memory Usage Guide for LatticeECP/EC and LatticeXP Devices

Introduction ........................................................................................................................................................ 9-1

Memories in LatticeECP/EC and LatticeXP Devices ......................................................................................... 9-1

Utilizing IPexpress.............................................................................................................................................. 9-3

IPexpress Flow.......................................................................................................................................... 9-3

Lattice Semiconductor

Table of Contents

LatticeXP Family Handbook

Memory Modules................................................................................................................................................ 9-7

Single Port RAM (RAM_DQ) – EBR Based .............................................................................................. 9-7

True Dual Port RAM (RAM_DP_TRUE) – EBR Based ........................................................................... 9-13

Pseudo Dual Port RAM (RAM_DP) – EBR-Based.................................................................................. 9-22

Read Only Memory (ROM) – EBR Based............................................................................................... 9-25

First In First Out (FIFO, FIFO_DC) – EBR Based................................................................................... 9-28

Distributed Single Port RAM (Distributed_SPRAM) – PFU Based.......................................................... 9-32

Distributed Dual Port RAM (Distributed_DPRAM) – PFU Based ............................................................ 9-35

Distributed ROM (Distributed_ROM) – PFU Based ................................................................................ 9-37

Initializing Memory ........................................................................................................................................... 9-39

Initialization File Format .......................................................................................................................... 9-39

Technical Support Assistance.......................................................................................................................... 9-41

Appendix A. Attribute Definitions...................................................................................................................... 9-42

DATA_WIDTH......................................................................................................................................... 9-42

REGMODE.............................................................................................................................................. 9-42

RESETMODE ......................................................................................................................................... 9-42

CSDECODE............................................................................................................................................ 9-42

WRITEMODE.......................................................................................................................................... 9-42

GSR ........................................................................................................................................................ 9-42

LatticeECP/EC and LatticeXP DDR Usage Guide

Introduction ...................................................................................................................................................... 10-1

DDR SDRAM Interfaces Overview................................................................................................................... 10-1

Implementing DDR Memory Interfaces with the LatticeECP/EC Devices........................................................ 10-2

DQS Grouping......................................................................................................................................... 10-2

DDR Software Primitives......................................................................................................................... 10-5

Memory Read Implementation ................................................................................................................ 10-9

Data Read Critical Path......................................................................................................................... 10-12

DQS Postamble .................................................................................................................................... 10-13

Memory Write Implementation .............................................................................................................. 10-14

Design Rules/Guidelines....................................................................................................................... 10-16

QDR II Interface .................................................................................................................................... 10-17

FCRAM (Fast Cycle Random Access Memory) Interface..................................................................... 10-17

Generic High Speed DDR Implementation .................................................................................................... 10-17

Board Design Guidelines ............................................................................................................................... 10-17

Technical Support Assistance........................................................................................................................ 10-18

Appendix A. Using IPexpress™ to Generate DDR Modules.......................................................................... 10-19

DDR Generic......................................................................................................................................... 10-19

DDR Memory Interface ......................................................................................................................... 10-20

Appendix B. Verilog Example for DDR Input and Output Modules ................................................................ 10-21

Appendix C. VHDL Example for DDR Input and Output Modules.................................................................. 10-23

Appendix D. Generic (Non-Memory) High-Speed DDR Interface .................................................................. 10-28

VHDL Implementation ........................................................................................................................... 10-28

Verilog Example .................................................................................................................................... 10-30

Preference File...................................................................................................................................... 10-31

Appendix E. List of Compatible DDR SDRAM ............................................................................................... 10-32

Appendix F. DDR400 Interface using the LatticeEC Evaluation Board.......................................................... 10-35

References..................................................................................................................................................... 10-36

LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide

Introduction ...................................................................................................................................................... 11-1

Features ........................................................................................................................................................... 11-1

Functional Description...................................................................................................................................... 11-1

PLL Divider and Delay Blocks................................................................................................................. 11-1

PLL Inputs and Outputs .......................................................................................................................... 11-2

PLL Attributes.......................................................................................................................................... 11-3

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