HY27SF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1Gb NAND FLASH
HY27SF081G2A
HY27SF161G2A
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.3 / Nov. 2006
1
HY27SF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.01
Initial Draft.
1) Change AC Conditions table
2) Change DC and Operating Characteristics
Test Conditions (
I
CC1
)
Before
After
Test Conditions (
I
OL
)
V
OL=
0.1V
V
OL=
0.2V
History
Draft Date
Mar. 16. 2006
Remark
Preliminary
t
RC
=30ns,
CE=
V
IL
, I
OUT
=0mA
t
RC
=50ns,
CE=
V
IL
, I
OUT
=0mA
Typ (
I
CC1
. I
CC2
, I
CC3
)
0.1
Before
After
Max (
I
CC1
. I
CC2
, I
CC3
)
30
20
Apr. 19. 2006
Preliminary
15
10
3) Change AC Timing Characteristics
4) Correct Supply Vlotage
Before
After
Vcc=1.65 to 1.95V
Vcc=1.70 to 1.95V
May. 18. 2006
Preliminary
0.2
1) Change NOP
1) Change 1Gb Package Type
- FBGA package is added
0.3
- Figure & dimension are changed
2) Delet Preliminary
3) Correct copy back function
Nov. 23. 2006
Rev 0.3 / Nov. 2006
2
HY27SF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle: Manufacturer Code
- 2nd cycle: Device Code
SUPPLY VOLTAGE
- VCC = 1.7 to 1.95V : HY27SFxx1G2A
Memory Cell Array
= (2K+64) Bytes x 64 Pages x 1,024 Blocks
= (1K+32) Words x 64 Pages x 1,024 Blocks
PAGE SIZE
- x8 device : (2K+64 spare) Bytes
: HY27SF081G2A
- x16 device : (1K+32 spare) Words
: HY27SF161G2A
DATA RETENTION
- 100,000 Program/Erase cycles (with 1bit/528byte ECC)
- 10 years Data Retention
PACKAGE
- HY27SF(08/16)1G2A-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27SF(08/16)1G2A-T (Lead)
- HY27SF(08/16)1G2A-TP (Lead Free)
- HY27SF081G2A-S(P)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27SF081G2A-S (Lead)
- HY27SF081G2A-SP (Lead Free)
- HY27SF081G2A-F(P)
: 63-Ball FBGA (9 x 11 x 1.0 mm)
- HY27SF081G2A-F (Lead)
- HY27SF081G2A-FP (Lead Free)
- 3rd cycle: Internal chip number, Cell Type, Number of
Simultaneously Programmed Pages.
- 4th cycle: Page size, Block size, Organization, Spare
size
SERIAL NUMBER OPTION
CHIP ENABLE DON’T CARE
- Simple interface with microcontroller
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 25us (max.)
- Sequential access: 50ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM
- Internal (2048+64) Byte buffer to improve the program
throughput
Rev 0.3 / Nov. 2006
3
HY27SF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The Hynix HY27SF(08/16)1G2A series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 1.8V Vcc
Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided
into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 1024 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data
input/output as well as command input. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Pro-
gram/Erase Controller automates all program and erase functions including pulse repetition, where required, and inter-
nal verification and margining of data.
The modify operations can be locked using the WP input pin or using the extended lock block feature described later.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27SF(08/16)1G2A extended reliability of 100K program/
erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
The chip could be offered with the CE don’t care function. This function allows the direct download of the code from
the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory. A cache read feature is also implemented. This feature allows to dramatically improve the read throughput
when consecutive pages have to be streamed out.
The HYNIX HY27SF(08/16)1G2A series is available in 48 - TSOP1 12 x 20 mm, 48 - USOP 12 x 17 mm, FBGA 9 x 11
mm.
1.1 Product List
PART NUMBER
HY27SF081G2A
HY27SF161G2A
ORIZATION
x8
x16
VCC RANGE
1.7V - 1.95 Volt
PACKAGE
63FBGA / 48TSOP1 / 48USOP1
48TSOP1
Rev 0.3 / Nov. 2006
4
HY27SF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
Data Inputs / Outputs (x16 Only)
Data Inputs / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Table 1: Signal Names
Rev 0.3 / Nov. 2006
5
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