IDT72215LB20J datasheet, PDF - EEWORLD Datasheet

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IDT72215LB20J: DescriptionFIFO, 512X18, 12ns, Synchronous, CMOS, PQCC68, 0.050 INCH PITCH, PLASTIC, LCC-68; Categorystorage storage; File Size209KB，21 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT72215LB20J Overview

FIFO, 512X18, 12ns, Synchronous, CMOS, PQCC68, 0.050 INCH PITCH, PLASTIC, LCC-68

IDT72215LB20J Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	LCC
package instruction	QCCJ, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	12 ns
Maximum clock frequency (fCLK)	50 MHz
period time	20 ns
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
length	24.2062 mm
memory density	9216 bit
Memory IC Type	OTHER FIFO
memory width	18
Humidity sensitivity level	1
Number of functions	1
Number of terminals	68
word count	512 words
character code	512
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512X18
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum standby current	0.07 A
Maximum slew rate	0.2 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	24.2062 mm

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CMOS SyncFIFO™

256 x 18, 512 x 18, 1024 x 18, 2048 x

18 and 4096 x 18

Integrated Device Technology, Inc.

IDT72205LB

IDT72215LB

IDT72225LB

IDT72235LB

IDT72245LB

FEATURES:

•

256 x 18-bit organization array (72205LB)

512 x 18-bit organization array (72215LB)

1024 x 18-bit organization array (72225LB)

2048 x 18-bit organization array (72235LB)

4096 x 18-bit organization array (72245LB)

15 ns read/write cycle time

Easily expandable in depth and width

Read and write clocks can be asynchronous or coincident

Dual-Port zero fall-through time architecture

Programmable almost-empty and almost-full flags

Empty and Full flags signal FIFO status

Half-Full flag capability in a single device configuration

Output enable puts output data bus in high-impedance

state

High-performance submicron CMOS technology

Available in a 64-lead thin quad flatpack (TQFP/STQFP),

pin grid array (PGA), and plastic leaded chip carrier

(PLCC)

Military product compliant to MIL-STD-883, Class B

Industrial temperature range (-40

C to +85

C) is avail-

able, tested to military electrical specifications

•

DESCRIPTION:

The IDT72205LB/72215LB/72225LB/72235LB/72245LB

are very high-speed, low-power First-In, First-Out (FIFO)

memories with clocked read and write controls. These FIFOs

are applicable for a wide variety of data buffering needs, such

as optical disk controllers, Local Area Networks (LANs), and

interprocessor communication.

Both FIFOs have 18-bit input and output ports. The input

port is controlled by a free-running clock (WCLK), and a data

input enable pin (

WEN

). Data is read into the synchronous

FIFO on every clock when

WEN

is asserted. The output port

is controlled by another clock pin (RCLK) and another enable

pin (

REN

). The read clock can be tied to the write clock for

single clock operation or the two clocks can run asynchronous

of one another for dual-clock operation. An Output Enable pin

(

) is provided on the read port for three-state control of the

output.

The synchronous FIFOs have two fixed flags, Empty (

)

and Full (

), and two programmable flags, Almost-Empty

(

PAE

) and Almost-Full (

PAF

). The offset loading of the pro-

grammable flags is controlled by a simple state machine, and

is initiated by asserting the Load pin (

). A Half-Full flag (

)

is available when the FIFO is used in a single device configu-

ration.

The IDT72205LB/72215LB/72225LB/72235LB/72245LB

are depth expandable using a daisy-chain technique. The XI

and

pins are used to expand the FIFOs. In depth expan-

sion configuration, FL is grounded on the first device and set

to HIGH for all other devices in the daisy chain.

The IDT72205LB/72215LB/72225LB/72235LB/72245LB is

fabricated using IDT’s high-speed submicron CMOS technol-

ogy. Military grade product is manufactured in compliance

with the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

WEN

WCLK

D0-D17

OFFSET REGISTER

INPUT REGISTER

WRITE CONTROL

LOGIC

WRITE POINTER

WXI

(

WXO

RXI

RXO

•

RAM ARRAY

256 x 18, 512 x 18

1024 x 18, 2048 x 18

4096 x 18

•

FLAG

LOGIC

PAF

PAE

WXO

)

READ POINTER

READ CONTROL

LOGIC

EXPANSION LOGIC

OUTPUT REGISTER

RESET LOGIC

Q0-Q17

RCLK

REN

2766 drw 01

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc.

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

DECEMBER 1996

DSC-2766/7

5.16

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