W29C040-15C datasheet, PDF - EEWORLD Datasheet

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W29C040-15C: DescriptionFlash, 512KX8, 150ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32; Categorystorage storage; File Size128KB，22 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W29C040-15C Overview

Flash, 512KX8, 150ns, PDIP32, 0.600 INCH, PLASTIC, DIP-32

W29C040-15C Parametric

Parameter Name	Attribute value
Maker	Winbond Electronics Corporation
Parts packaging code	DIP
package instruction	0.600 INCH, PLASTIC, DIP-32
Contacts	32
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	150 ns
JESD-30 code	R-PDIP-T32
JESD-609 code	e3
length	41.91 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	5.33 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
type	NOR TYPE
width	15.24 mm
Maximum write cycle time (tWC)	10 ms

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Preliminary W29C040

512K

8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29C040 is a 4-megabit, 5-volt only CMOS page mode EEPROM organized as 512K

8 bits.

The device can be written (erased and programmed) in-system with a standard 5V power supply. A

12-volt V

is not required. The unique cell architecture of the W29C040 results in fast write (erase/

program) operations with extremely low current consumption compared to other comparable 5-volt

flash memory products. The device can also be written (erased and programmed) by using standard

EPROM programmers.

FEATURES

•

Single 5-volt write (erase and program)

operations

Fast page-write operations

−

256 bytes per page

−

Page write (erase/program) cycle: 5 mS

(typ.)

−

Effective byte-write (erase/program) cycle

time: 19.5

µS

−

Optional software-protected data write

•

Low power consumption

−

Active current: 25 mA (typ.)

−

Standby current: 20

µA

(typ.)

•

Automatic write (erase/program) timing with

internal V

generation

End of write (erase/program) detection

−

Toggle bit

−

Data polling

•

Fast chip-erase operation: 50 mS

Two 16 KB boot blocks with lockout

Typical Page write (erase/program) cycles:

1K/10K/100K (typ.)

Read access time: 90/120/150 nS

Ten-year data retention

Software and hardware data protection

•

Latched address and data

All inputs and outputs directly TTL compatible

JEDEC standard byte-wide pinouts

Available packages: 32-pin 600 mil DIP, 450

mil

SOP, TSOP, and PLCC

-1-

Publication Release Date: April 1997

Revision A1

Preliminary W29C040

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29C040 is controlled by CE and OE , both Chip of which have to be low

for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the

chip is de-selected and only standby power will be consumed. OE is the output control and is used to

gate data from the output pins. The data bus is in high impedance state when either CE or OE is

high.

Refer to the read cycle timing waveforms for further details.

Page Write Mode

The W29C040 is written (erased/programmed) on a page basis. Every page contains 256 bytes of

data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the

device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure

consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the

device.

Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are

simultaneously written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE ,

whichever occurs last. The data are latched by the rising edge of either CE or WE , whichever

occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (T

BLC

) of

200

µS

after the initial byte-load cycle, the W29C040 will stay in the page load cycle. Additional bytes

can then be loaded consecutively. The page load cycle will be terminated and the internal write

(erase/program) cycle will start if no additional byte is loaded into the page buffer. A8 to A18 specify

the page address. All bytes that are loaded into the page buffer must have the same page address.

A0 to A7 specify the byte address within the page. The bytes may be loaded in any order; sequential

loading is not required.

In the internal write cycle, all data in the page buffers, i.e., 256 bytes of data, are written

simultaneously into the memory array. The typical write (erase/program) time is 5 mS. The entire

memory array can be written in 10.4 seconds. Before the completion of the internal write cycle, the

host is free to perform other tasks such as fetching data from other locations in the system to prepare

to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is

enabled, any write operation requires a three-byte command sequence (with specific data to a

specific address) to be performed before the data load operation. The three-byte load command

sequence begins the page load cycle, without which the write operation will not be activated. This

write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by

noise during system power-up and power-down.

The W29C040 is shipped with the software data protection enabled. To enable the software data

protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The

Publication Release Date: April 1997

Revision A1

-3-

Preliminary W29C040

device will then enter the software data protection mode, and any subsequent write operation must be

preceded by the three-byte command sequence cycle. Once enabled, the software data protection

will remain enabled unless the disable commands are issued. A power transition will not reset the

software data protection feature. To reset the device to unprotected mode, a six byte command

sequence is required. For information about specific codes, see the Command Codes for Software

Data Protection in the Table of Operating Modes. For information about timing waveforms, see the

timing diagrams below.

Hardware Data Protection

The integrity of the data stored in the W29C040 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The write operation is inhibited when V

is less than 2.5V.

(3) Write Inhibit Mode: Forcing

low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reach its sense level, the device will automatically time-out 5

mS before any write (erase/program) operation.

Chip Erase Modes

The entire device can be erased by using a six-byte software command code. See the Software Chip

Erase Timing Diagram.

Boot Block Operation

There are two boot blocks (16K bytes each) in this device, which can be used to store boot code. One

of them is located in the first 16K bytes and the other is located in the last 16K bytes of the memory.

The first 16K or last 16K of the memory can be set as a boot block by using a seven-byte command

sequence.

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set

the data for the designated block cannot be erased or programmed (programming lockout); other

memory locations can be changed by the regular programming method. Once the boot block

programming lockout feature is activated, the chip erase function will be disabled. In order to detect

whether the boot block feature is set on the two 16K blocks, users can perform a six-byte command

sequence: enter the product identification mode (see Command Codes for Identification/Boot Block

Lockout Detection for specific code), and then read from address "00002 hex" (for the first 16K bytes)

or "3FFF2 hex" (for the last 16K bytes). If the output data is "FF hex," the boot block programming

lockout feature is activated; if the output data is "FE hex," the lockout feature is inactivated and the

block can be programmed.

To return to normal operation, perform a three-byte command sequence to exit the identification

mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.

Data Polling (DQ7)- Write Status Detection

The W29C040 includes a data polling feature to indicate the end of a write cycle. When the

W29C040 is in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the

page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed.

DQ7 will show the true data. See the DATA Polling Timing Diagram.

-4-

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