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CY7C017A-12JXC

Description
Dual-Port SRAM, 32KX9, 12ns, CMOS, PQCC68, PLASTIC, LCC-68
Categorystorage    storage   
File Size3MB,20 Pages
ManufacturerCypress Semiconductor
Environmental Compliance  
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CY7C017A-12JXC Overview

Dual-Port SRAM, 32KX9, 12ns, CMOS, PQCC68, PLASTIC, LCC-68

CY7C017A-12JXC Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerCypress Semiconductor
Parts packaging codeLCC
package instructionQCCJ,
Contacts68
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time12 ns
JESD-30 codeS-PQCC-J68
JESD-609 codee3
length24.2316 mm
memory density294912 bit
Memory IC TypeDUAL-PORT SRAM
memory width9
Humidity sensitivity level3
Number of functions1
Number of terminals68
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX9
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width24.2316 mm
CY7C006A
CY7C007A
CY7C017A32K/16K x 8, 32K x 9
Dual-Port Static RAM
CY7C006A/CY7C007A
CY7C016A/CY7C017A
32K/16K x 8, 32K x 9
Dual-Port Static RAM
Features
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12
[1]
/15/20 ns
• Low operating power
— Active: I
CC
= 180 mA (typical)
— Standby: I
SB3
= 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
• Pb-Free packages available
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
[2]
8/9
8/9
[2]
I/O
0L
–I/O
7/8L
I/O
Control
I/O
Control
I/O
0R
–I/O
7/8R
14/15
[4]
A
0L
–A
13/14L
Address
Decode
14/15
True Dual-Ported
RAM Array
Address
Decode
14/15
14/15
A
0R
–A
13/14R
[4]
[4]
A
0L
–A
13/14L
CE
L
OE
L
R/W
L
SEM
L
Interrupt
Semaphore
Arbitration
BUSY
L
INT
L
[3]
A
0R
–A
13/14R
CE
R
OE
R
R/W
R
SEM
R
[3]
[4]
BUSY
R
INT
R
M/S
Notes:
1. See page 7 for Load Conditions.
2. I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices.
3. BUSY is an output in master mode and an input in slave mode.
4. A
0
–A
13
for 16K; A
0
–A
14
for 32K devices.
Cypress Semiconductor Corporation
Document #: 38-06045 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 11, 2005
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CY7C017A-12JXC Related Products

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Description Dual-Port SRAM, 32KX9, 12ns, CMOS, PQCC68, PLASTIC, LCC-68 Dual-Port SRAM, 32KX9, 20ns, CMOS, PQCC68, PLASTIC, LCC-68 Dual-Port SRAM, 16KX9, 20ns, CMOS, PQFP80, PLASTIC, TQFP-80 Dual-Port SRAM, 16KX9, 12ns, CMOS, PQFP80, PLASTIC, TQFP-80 Dual-Port SRAM, 32KX8, 12ns, CMOS, PQCC68, PLASTIC, LCC-68 Dual-Port SRAM, 32KX8, 12ns, CMOS, PQFP80, PLASTIC, TQFP-80 Dual-Port SRAM, 32KX9, 15ns, CMOS, PQCC68, PLASTIC, LCC-68
Parts packaging code LCC LCC QFP QFP LCC QFP LCC
package instruction QCCJ, QCCJ, LQFP, PLASTIC, TQFP-80 PLASTIC, LCC-68 PLASTIC, TQFP-80 QCCJ,
Contacts 68 68 80 80 68 80 68
Reach Compliance Code compliant compliant unknown compliant compliant compliant compliant
ECCN code 3A991.B.2.B 3A991.B.2.B EAR99 EAR99 EAR99 EAR99 3A991.B.2.B
Maximum access time 12 ns 20 ns 20 ns 12 ns 12 ns 12 ns 15 ns
JESD-30 code S-PQCC-J68 S-PQCC-J68 S-PQFP-G80 S-PQFP-G80 S-PQCC-J68 S-PQFP-G80 S-PQCC-J68
length 24.2316 mm 24.2316 mm 14 mm 14 mm 24.2316 mm 14 mm 24.2316 mm
memory density 294912 bit 294912 bit 147456 bit 147456 bit 262144 bit 262144 bit 294912 bit
Memory IC Type DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM
memory width 9 9 9 9 8 8 9
Number of functions 1 1 1 1 1 1 1
Number of terminals 68 68 80 80 68 80 68
word count 32768 words 32768 words 16384 words 16384 words 32768 words 32768 words 32768 words
character code 32000 32000 16000 16000 32000 32000 32000
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
organize 32KX9 32KX9 16KX9 16KX9 32KX8 32KX8 32KX9
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code QCCJ QCCJ LQFP LQFP QCCJ LQFP QCCJ
Package shape SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
Package form CHIP CARRIER CHIP CARRIER FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE CHIP CARRIER FLATPACK, LOW PROFILE CHIP CARRIER
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 5.08 mm 5.08 mm 1.6 mm 1.6 mm 5.08 mm 1.6 mm 5.08 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form J BEND J BEND GULL WING GULL WING J BEND GULL WING J BEND
Terminal pitch 1.27 mm 1.27 mm 0.65 mm 0.65 mm 1.27 mm 0.65 mm 1.27 mm
Terminal location QUAD QUAD QUAD QUAD QUAD QUAD QUAD
width 24.2316 mm 24.2316 mm 14 mm 14 mm 24.2316 mm 14 mm 24.2316 mm
Is it lead-free? Lead free Lead free - - Lead free Lead free Lead free
Is it Rohs certified? conform to conform to - conform to conform to conform to conform to
Maker Cypress Semiconductor Cypress Semiconductor - Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor
JESD-609 code e3 e3 - e3 e3 e3 e3
Humidity sensitivity level 3 3 - - 3 3 3
Peak Reflow Temperature (Celsius) 260 260 - 260 260 260 260
Terminal surface Matte Tin (Sn) Matte Tin (Sn) - Tin (Sn) Matte Tin (Sn) Tin (Sn) Matte Tin (Sn)
Maximum time at peak reflow temperature 20 20 - 20 20 20 20
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