NM93C06/C46/C56/C66 256-/1024-/2048-/4096-Bit Serial EEPROM (MICROWIRE Bus Interface)
NM93C06/C46/C56/C66
March 1997
NM93C06/C46/C56/C66
256-/1024-/2048-/4096-Bit Serial EEPROM (MICROWIRE
™
Bus Interface)
General Description
The NM93C06/C46/C56/C66 devices are 256/1024/2048/
4096 bits, respectively, of CMOS non-volatile electrically
erasable memory divided into 16/64/128/256 16-bit regis-
ters. They are fabricated using Fairchild Semiconductor’s
floating-gate CMOS process for high reliability and low
power consumption. These memory devices are available in
both SO and TSSOP packages for small space consider-
ations.
The EEPROM Interfacing is MICROWIRE compatible for
simple interface to standard microcontrollers and micropro-
cessors. There are 7 instructions that control these devices:
Read, Erase/Write Enable, Erase, Erase All, Write, Write All,
and Erase/Write Disable. The ready/busy status is available
on the DO pin during programming.
Features
n
Device status during programming mode
n
Typical active current of 200 µA; Typical standby current
of 10 µA
n
No erase required before write
n
Reliable CMOS floating gate technology
n
4.5V to 5.5V operation in all modes
n
MICROWIRE compatible serial I/O
n
Self-timed programming cycle
n
40 years data retention
n
Endurance: 10
6
data changes
n
Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Block Diagram
DS010751-1
© 1997 Fairchild Semiconductor Corporation
DS010751
www.fairchildsemi.com
1
PrintDate=1997/08/29 PrintTime=11:28:40 10393 ds010751 Rev. No. 3 cmserv
Proof
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Capacitance
T
A
= 25˚C f = 1 MHz
Symbol
C
OUT
C
IN
Test
Output Capacitance
Input Capacitance
Typ
Max
5
5
Units
pF
pF
Note 1:
Throughout this table, “M” refers to temperature range (−55˚C to +125˚C), not package.
Note 2:
Stress ratings above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and operation
of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Note 3:
CS (Chip Select) must be brought low (to V
IL
) for an interval of t
CS
in order to reset all internal device registers (device reset) prior to beginning another
opcode cycle (This is shown in the opcode diagrams in the following pages).
Note 4:
Typical leakage values are in the 20 nA range.
Note 5:
The shortest allowable SK clock period = 1/f
SK
(as shown under the f
SK
parameter). Maximum SK clock speed (minimum SK period) is determined by the
interaction of several AC parameters stated in the datasheet. Within this SK period, both t
SKH
and t
SKL
limits must be observed. Therefore, it is not allowable to set
1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 6:
Throughout this table, “M” refers to temperature range (-55˚C to = 125˚C), not package.
AC Test Conditions
V
CC
Range
4.5V
≤
V
CC
≤
5.5V
(TTL Levels)
Output Load: 1 TTL Gate (C
L
= 100 pF)
V
IL
/V
IH
Input Levels
0.4V/2.4V
V
IL
/V
IH
Timing Level
1.0V/2.0V
V
OL
/V
OH
Timing Level
0.4V/2.4V
−2.1 mA/0.4 mA
I
OL
/I
OH
Functional Description
The NM93C06/C46/C56/C66 devices have 7 instructions as
described below. Note that the MSB of any instruction is a “1”
and is viewed as a start bit in the interface sequence. For the
C06 and C46 the next 8 bits carry the op code and the 6-bit
address for register selection. For the C56 and C66 the next
10-bits carry the op code and the 8-bit address for register
selection.
All Data in signals are clocked into the device on the
low-to-high SK transition.
Read (READ):
The READ instruction outputs serial data on the DO pin. Af-
ter a READ instruction is received, the instruction and ad-
dress are decoded, followed by data transfer from the se-
lected memory register into a 16-bit serial-out shift register. A
dummy bit (logical 0) precedes the 16-bit data output string.
Output data changes are initiated by a low to high transition
of the SK clock.
Erase/Write Enable (WEN):
When V
CC
is applied to the part, it powers up in the Erase/
Write Disable (WDS) state. Therefore, all programming
modes must be preceded by an Erase/Write Enable WEN in-
struction. Once an Erase/Write Enable instruction is ex-
ecuted, programming remains enabled until an Erase/Write
Disable (WDS) instruction is executed or V
CC
is completely
removed from the part.
Erase (ERASE):
The ERASE instruction will program all bits in the selected
register to the logical “1” state. CS is brought low following
the loading of the last address bit. This falling edge of the CS
pin initiates the self-timed programming cycle.
The DO pin indicates the READY/BUSY status of the chip if
CS is brought high after the t
CS
interval. DO = logical “0” in-
dicates that programming is still in progress. DO = logical “1”
indicates that the register, at the address specified in the in-
struction, has been erased, and the part is ready for another
instruction.
www.fairchildsemi.com
4
Write (WRITE):
The WRITE instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data is
put on the data-in (DI) pin, CS must be brought low before
the next rising edge of the SK clock. This falling edge of CS
initiates the self-timed programming cycle. The DO pin indi-
cates the READY/BUSY status of the chip if CS is brought
high after the t
CS
interval. DO = logical 0 indicates that pro-
gramming is still in progress. DO = logical 1 indicates that
the register at the address specified in the instruction has
been written with the data pattern specified in the instruction
and the part is ready for another instruction.
Erase All (ERAL):
The ERAL instruction will simultaneously program all regis-
ters in the memory array and set each bit to the logical “1”
state. The Erase All cycle is identical to the ERASE cycle ex-
cept for the different op-code. As in the ERASE mode, the
DO pin indicates the READY/BUSY status of the chip if CS is
brought high after the t
CS
interval.
Write All (WRALL):
The WRALL instruction will simultaneously program all regis-
ters with the data pattern specified in the instruction. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after the t
CS
interval.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruc-
tion disables all programming modes and should follow all
programming operations. Execution of a READ instruction is
independent of both the WEN and WDS instructions.
Note:
The NSC CMOS EEPROMs do not require an “ERASE” or “ERASE
ALL” operation prior to the “WRITE” and “WRITE ALL” instructions.
The “ERASE” and “ERASE ALL” instructions are included to maintain
compatibility with earlier technology EEPROMs.
PrintDate=1997/08/29 PrintTime=11:28:44 10393 ds010751 Rev. No. 3
cmserv
Proof
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