PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors;
R1 = 10 k, R2 = 10 k
Rev. 11 — 25 September 2013
Product data sheet
1. Product profile
1.1 General description
NPN/PNP Resistor-Equipped Transistors (RET) in Surface-Mounted Device (SMD) plastic
packages.
Table 1.
Product overview
Package
NXP
PEMD3
PIMD3
PUMD3
SOT666
SOT457
SOT363
JEITA
-
SC-74
SC-88
PNP/PNP
complement
PEMB11
-
PUMB11
NPN/NPN
complement
PEMH11
-
PUMH11
Package
configuration
ultra small and flat lead
small
very small
Type number
1.2 Features and benefits
100 mA output current capability
Built-in bias resistors
Simplifies circuit design
Reduces component count
Reduces pick and place costs
AEC-Q101 qualified
1.3 Applications
Low current peripheral driver
Control of IC inputs
Replaces general-purpose transistors in digital applications
1.4 Quick reference data
Table 2.
Symbol
V
CEO
I
O
R1
R2/R1
Quick reference data
Parameter
collector-emitter voltage
output current
bias resistor 1 (input)
bias resistor ratio
Conditions
open base
Min
-
-
7
0.8
Typ
-
-
10
1
Max
50
100
13
1.2
Unit
V
mA
k
Per transistor; for the PNP transistor (TR2) with negative polarity
NXP Semiconductors
PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors
2. Pinning information
Table 3.
Pin
1
2
3
4
5
6
Pinning
Description
GND (emitter) TR1
input (base) TR1
output (collector) TR2
GND (emitter) TR2
input (base) TR2
output (collector) TR1
1
2
3
001aab555
TR1
R2
R1
R1
R2
TR2
Simplified outline
6
5
4
Graphic symbol
6
5
4
1
2
3
006aaa143
3. Ordering information
Table 4.
Ordering information
Package
Name
PEMD3
PIMD3
PUMD3
-
SC-74
SC-88
Description
plastic surface-mounted package; 6 leads
plastic surface-mounted package (TSOP6); 6 leads
plastic surface-mounted package; 6 leads
Version
SOT666
SOT457
SOT363
Type number
4. Marking
Table 5.
PEMD3
PIMD3
PUMD3
[1]
Marking codes
Marking code
[1]
D3
M7
D*3
Type number
* = placeholder for manufacturing site code.
PEMD3_PIMD3_PUMD3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 25 September 2013
2 of 18
NXP Semiconductors
PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
V
EBO
V
I
Parameter
collector-base voltage
collector-emitter voltage
emitter-base voltage
input voltage TR1
positive
negative
input voltage TR2
positive
negative
I
O
I
CM
P
tot
output current
peak collector current
total power dissipation
PEMD3 (SOT666)
PIMD3 (SOT457)
PUMD3 (SOT363)
Per device
P
tot
total power dissipation
PEMD3 (SOT666)
PIMD3 (SOT457)
PUMD3 (SOT363)
T
j
T
amb
T
stg
[1]
Conditions
open emitter
open base
open collector
Min
-
-
-
-
-
-
-
-
-
Max
50
50
10
+40
10
+10
40
100
100
200
250
200
Unit
V
V
V
V
V
V
V
mA
mA
mW
mW
mW
Per transistor; for the PNP transistor (TR2) with negative polarity
T
amb
25
C
[1]
-
-
-
T
amb
25
C
[1]
-
-
-
-
65
65
300
400
300
150
+150
+150
mW
mW
mW
C
C
C
junction temperature
ambient temperature
storage temperature
Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
PEMD3_PIMD3_PUMD3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 25 September 2013
3 of 18
NXP Semiconductors
PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors
500
P
tot
(mW)
400
006aac766
(1)
(2)
300
200
100
0
-75
-25
25
75
125
175
T
amb
(°C)
(1) SOT457; FR4 PCB, standard footprint
(2) SOT363 and SOT666; FR4 PCB, standard footprint
Fig 1.
Per device: Power derating curves
6. Thermal characteristics
Table 7.
Symbol
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to ambient
PEMD3 (SOT666)
PIMD3 (SOT457)
PUMD3 (SOT363)
Per device
R
th(j-a)
thermal resistance from
junction to ambient
PEMD3 (SOT666)
PIMD3 (SOT457)
PUMD3 (SOT363)
[1]
Conditions
in free air
[1]
Min
Typ
Max
Unit
Per transistor
-
-
-
in free air
[1]
-
-
-
625
500
625
K/W
K/W
K/W
-
-
-
-
-
-
417
313
417
K/W
K/W
K/W
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
PEMD3_PIMD3_PUMD3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 25 September 2013
4 of 18
NXP Semiconductors
PEMD3; PIMD3; PUMD3
NPN/PNP resistor-equipped transistors
10
3
duty cycle = 1
Z
th(j-a)
(K/W)
10
2
0.1
0.05
0.02
0.01
0.75
0.5
0.33
0.2
006aac751
10
0
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig 2.
Transient thermal impedance from junction to ambient as a function of pulse duration for
PEMD3 (SOT666); typical values
006aac767
10
3
duty cycle = 1
Z
th(j-a)
(K/W)
10
2
0.1
0.05
0.02
0.01
0.75
0.5
0.33
0.2
10
0
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB, standard footprint
Fig 3.
Transient thermal impedance from junction to ambient as a function of pulse duration for
PIMD3 (SOT457); typical values
PEMD3_PIMD3_PUMD3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 25 September 2013
5 of 18
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