preliminary
Data Sheet
Rev.0.9
26.07.2013
4096MB DDR3L
– SDRAM ECC SO-DIMM
204 Pin ECC SO-UDIMM
SLN04G72G2BF2HY-xxRT
4GByte in FBGA Technology
RoHS compliant
Features:
204-pin 72-bit DDR3 Small Outline, Dual-In-Line Double
Data Rate synchronous DRAM Module
Module organization: dual rank 512M x 72
V
DD
= 1.35V and 1.5V
V
DDQ
= 1.35V and 1.5V
SSTL_15 compatible
Fly-by-bus with termination for C/A & CLK bus
2
On-board I C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
Gold-contact pad
This module is fully pin and functional compatible to the
JEDEC EP3-12800 DDR3 SDRAM 72bit-SO-DIMM
design spec. and JEDEC- Standard MO-268. (see
www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
DDR3 - SDRAM component Hynix
H5TC2G83FFR-PBA
256Mx8 DDR3 SDRAM in PG-TFBGA-78 package
8-bit prefetch architecture
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
On-Die-Termination (ODT) and Dynamic ODT for
improved signal integrity.
Refresh, Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write
Leveling and Multi Purpose Register (MPR) Read Pattern.
Options:
Data Rate / Latency
DDR3 1333 MT/s CL9
DDR3 1600 MT/s CL11
Module density
4096MB with 18 dies and 2 ranks
Standard Grade
(T
A
)
(T
C
)
0°C to 70°C
0°C to 85°C
Marking
-CC
-DC
*) The refresh rate has to be doubled when 85°C<T
C
<95°C
Environmental Requirements:
Operating temperature (ambient)
Standard Grade
0°C to 70°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Figure:
mechanical dimensions
1
1
if no tolerances specified ± 0.15mm
Page 1
of 17
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
preliminary
Data Sheet
Rev.0.9
26.07.2013
This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM ECC Small Outline Dual-In-line
Memory Module (SO-UDIMM) which is organized as x72 high speed CMOS memory arrays. The module uses
internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to
achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ
and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. The burst length is either four or
eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated
at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent
operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-
down” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
2
using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
512M x 72bit
DDR3 SDRAMs used
18 x 256M x 8bit (2Gbit)
Row
Addr.
15
Device Bank
Addr.
BA0, BA1, BA2
Column
Refresh
Addr.
10
8k
Module
Bank Select
S0#, S1#
Module Dimensions
in mm
67.60 (long) x 30(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
SLN04G72G2BF2HY-CCRT
SLN04G72G2BF2HY-DCRT
Module Density
4GByte
4GByte
Transfer Rate
10.6 GB/s
12.8 GB/s
Clock Cycle/Data bit rate
1.5ns/1333MT/s
1.25ns/1600MT/s
Latency
9-9-9
11-11-11
Pin Name
A0 – A9, A11 – A14
A10/AP
BA0 – BA2
DQ0 – DQ63
CB0 – CB07
DM0 – DM8
DQS0 – DQS8
DQS0# – DQS8#
RAS#
CAS#
WE#
CKE0 – CKE1
S0#, S1#
CK0 – CK1
CK0# – CK1#
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Address Inputs
Address Input / Autoprecharge Bit
Bank Address Inputs
Data Input / Output
ECC check bits
Input Data Mask
Data Strobe, positive line
Data Strobe, negative line (only used when differential data strobe mode is enabled)
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Chip Select
Clock Inputs, positive line
Clock Inputs, negative line
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 2
of 17
preliminary
Data Sheet
Rev.0.9
26.07.2013
Event#
V
DD
V
REF
DQ
V
REF
CA
V
SS
V
TT
V
DDSPD
SCL
SDA
SA0 – SA1
ODT0, ODT1
NC
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
Supply Voltage (1.35V -0.067V/+0.1V and 1.5V ± 0.075V)
Reference voltage: DQ, DM (V
DD
/2)
Reference voltage: Control, command, and address (V
DD
/2)
Ground
Termination voltage: Used for control, command, and address (V
DD
/2).
Serial EEPROM Positive Power Supply
Serial Clock for Presence Detect
Serial Data Out for Presence Detect
Presence Detect Address Inputs
On-Die Termination
No Connection
Pin Configuration
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
Symbol
V
REFDQ
V
SS
DQ0
DQ1
V
SS
DM0
DQ2
DQ3
VSS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
PIN
53
55
57
59
61
63
65
67
69
71
Key
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
Frontside
Symbol
PIN
V
SS
DQ24
DQ25
DM3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
DD
CKE0
CKE1
BA2
V
DD
A12/BC#
A8
A5
V
DD
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
Symbol
A3
A1
A0
V
DD
CK0
CK0#
V
DD
A10/AP
BA0
WE#
V
DD
CAS#
S0#
S1#
V
DD
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
PIN
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
Symbol
V
SS
DM5
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
DQ58
DQ59
V
SS
SA0
V
DDSPD
SA1
V
TT
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 3
of 17
preliminary
Data Sheet
Rev.0.9
26.07.2013
Backside
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
Symbol
V
SS
DQ4
DQ5
V
SS
DQS0#
DQS0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
Reset#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
DM2
V
SS
DQ22
DQ23
V
SS
Pin
54
56
58
60
62
64
66
68
70
72
Key
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
Symbol
DQ28
DQ29
V
SS
DQS3#
DQS3
V
SS
DQ30
DQ31
V
SS
CB4
Pin
104
106
108
110
112
114
116
118
120
122
124
Symbol
A4
A2
BA1
V
DD
CK1
CK1#
V
DD
NC(S3#)
NC(S2#)
RAS#
V
DD
ODT0
ODT1
A13
V
DD
DQ36
DQ37
V
SS
DM4
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
Pin
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
Symbol
DQS5
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
EVENT#
SDA
SCL
V
TT
CB5
DM8
V
SS
CB6
CB7
V
REFCA
V
DD
NC(A15)
A14
A9
V
DD
A11
A7
A6
V
DD
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 4
of 17
preliminary
Data Sheet
Rev.0.9
26.07.2013
FUNCTIONAL BLOCK DIAGRAMM 4096MB DDR3 SDRAM SO-UDIMM,
2 RANK AND 18 COMPONENTS
S1
S0
DQS0
DQS0
DM0
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DQS4
DM4
DM
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS DQS
D0
D9
D4
D13
ZQ
ZQ
ZQ
ZQ
DQS1
DQS1
DM1
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS DQS
DQS5
DQS5
DM5
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS DQS
D1
D10
D5
D14
ZQ
ZQ
ZQ
ZQ
DQS2
DQS2
DM2
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS DQS
DQS6
DQS6
DM6
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS DQS
D2
D11
D6
D15
ZQ
ZQ
ZQ
ZQ
DQS3
DQS3
DM3
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS DQS
DQS7
DQS7
DM7
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS DQS
D3
D12
D7
D16
ZQ
ZQ
ZQ
ZQ
DQS8
DQS8
DM8
DM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
CS
DQS DQS
V
DDSPD
V
DD/
V
DDQ
V
REFDQ
V
REFCA
V
SS
SPD
D0-D17
D0-D17
D0-D17
D0-D17
D8
D17
ZQ
ZQ
BA0-BA2
A0-A14
RAS
CAS
WE
ODT0
ODT1
CKE0
CKE1
CK0,CK1
CK0,CK1
RESET
BA0-BA2: SDRAM D0-D17
A0-A14: SDRAM D0-D17
RAS: SDRAM D0-D17
CAS: SDRAM D0-D17
WE: SDRAM D0-D17
ODT: SDRAM D0-D8
ODT: SDRAM D9-D17
CKE: SDRAM D0-D8
CKE: SDRAM D9-D17
CK: SDRAM D0-D17
CK: SDRAM D0-D17
RESET: SDRAM D0-D17
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be
maintained as shown.
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
4. Refer to the appropriate clock wiring topology under
the DIMM wiring details section of the JEDED document.
5. For each DRAM, a unique ZQ resistor is connected to
GND. The ZQ resistor is 240O±1%.
6. Refer to associated figure for SPD details.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: info@swissbit.com
Page 5
of 17
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