PIC16(L)F15354/55
Full-Featured 28-Pin Microcontrollers
Description
PIC16(L)F15354/55 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
The devices feature multiple PWMs, multiple communication, temperature sensor, and memory features like Memory
Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information
Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy.
Core Features
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Timers:
- 8-bit Timer2 with Hardware Limit Timer (HLT)
- 16-bit Timer0/1
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
- Variable prescaler selection
- Variable window size selection
- All sources configurable in hardware or
software
• Programmable Code Protection
Power-Saving Functionality
• DOZE mode: Ability to Run the CPU Core Slower
than the System Clock
• IDLE mode: Ability to halt CPU Core while Internal
Peripherals Continue Operating
• SLEEP mode: Lowest Power Consumption
• Peripheral Module Disable (PMD):
- Ability to disable hardware module to
minimize active power consumption of
unused peripherals
eXtreme Low-Power (XLP) Features
•
•
•
•
Sleep mode: 50 nA @ 1.8V, typical
Watchdog Timer: 500 nA @ 1.8V, typical
Secondary Oscillator: 500 nA @ 32 kHz
Operating Current:
- 8
A
@ 32 kHz, 1.8V, typical
- 32
A/MHz
@ 1.8V, typical
Digital Peripherals
• Four Configurable Logic Cells (CLC):
- Integrated combinational and sequential logic
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
• Two Capture/Compare/PWM (CCP) module:
- 16-bit resolution for Capture/Compare modes
- 10-bit resolution for PWM mode
• Four 10-Bit PWMs
• Numerically Controlled Oscillator (NCO):
- Generates true linear frequency control and
increased frequency resolution
- Input Clock: 0 Hz < F
NCO
< 32 MHz
- Resolution: F
NCO
/2
20
• Communication:
- Up to two EUSART, RS-232, RS-485, LIN
compatible
- Up to two SPI
- Two I
2
C, SMBus, PMBus™ compatible
Memory
•
•
•
•
Up to 14 KB Flash Program Memory
Up to 1 KB Data SRAM
Direct, Indirect and Relative Addressing modes
Memory Access Partition (MAP):
- Write protect
- Customizable Partition
• Device Information Area (DIA)
• Device Configuration Information (DCI)
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF15354/55)
- 2.3V to 5.5V (PIC16F15354/55)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
2016 Microchip Technology Inc.
Preliminary
DS40001853A-page 1
PIC16(L)F15354/55
Digital Peripherals (Cont.)
• I/O Pins:
- Individually programmable pull-ups
- Slew rate control
- Interrupt-on-change with edge-select
- Input level selection control (ST or TTL)
- Digital open-drain enable
- Current mode enable
• Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
Flexible Oscillator Structure
• High-Precision Internal Oscillator:
- Software selectable frequency range up to 32
MHz, ±1% typical
• x2/x4 PLL with Internal and External Sources
• Low-Power Internal 32 kHz Oscillator
(LFINTOSC)
• External 32 kHz Crystal Oscillator (SOSC)
• External Oscillator Block with:
- Three crystal/resonator modes up to 20 MHz
- Three external clock modes up to 32 MHz
• Fail-Safe Clock Monitor:
- Allows for safe shutdown if primary clock
stops
• Oscillator Start-up Timer (OST):
- Ensures stability of crystal oscillator
resources
Analog Peripherals
• Analog-to-Digital Converter (ADC):
- 10-bit with up to 43 external channels
- Operates in Sleep
• Two Comparators:
- FVR, DAC and external input pin available on
inverting and noninverting input
- Software selectable hysteresis
- Outputs available internally to other modules,
or externally through PPS
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
• Zero-Cross Detect module
- AC high voltage zero-crossing detection for
simplifying TRIAC control
- Synchronized switching control and timing
DS40001853A-page 2
Preliminary
2016 Microchip Technology Inc.
PIC16(L)F15354/55
TABLE 1:
PIC16(L)F153XX FAMILY TYPES
Program Flash Memory (KW)
Program Flash Memory (KB)
Peripheral Module Disable
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Memory Access Partition
Window Watchdog Timer
Device Information Area
Storage Area Flash (B)
8-bit/ (with HLT) Timer
Peripheral Pin Select
Zero-Cross Detect
Temperature Sensor
Data Sheet Index
CCP/10-bit PWM
EUSART/ MSSP
Comparator
16-bit Timer
Data SRAM
(bytes)
10-bit ADC
5-bit DAC
Device
PIC16(L)F15313
(C)
2
PIC16(L)F15323
(C)
2
PIC16(L)F15324
(D)
4
PIC16(L)F15325
(B)
8
PIC16(L)F15344
(D)
4
PIC16(L)F15345
(B)
8
PIC16(L)F15354
(A)
4
PIC16(L)F15355
(A)
8
PIC16(L)F15356
(E)
16
PIC16(L)F15375
(E)
8
PIC16(L)F15376
(E)
16
PIC16(L)F15385
(E)
8
PIC16(L)F15386
(E)
16
Note 1:
Data Sheet Index:
A:
DS40001853
B:
Future Release
C:
Future Release
D:
Future Release
E:
Note:
Future Release
3.5 224 256
3.5 224 256
7
14
7
14
7
14
28
14
28
14
28
224 512
224 512
224 512
6
12
12
18
25
5
11
11
11
17
17
24
24
24
35
35
43
43
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2/4 1
2/4 1
2/4 1
2/4 1
2/4 1
2/4 1
2/4 1
2/4 1
2/4 1
2/4 1
2/4 1
2/4 1
2/4 1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
4
4
4
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y Y Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1/1 Y
1/1 Y
2/1 Y
2/1 Y
2/1 Y
2/1 Y
2/2 Y
2/2 Y
2/2 Y
2/2 Y
2/2 Y
2/2 Y
2/2 Y
I
I
I
I
I
I
I
I
I
I
I
I
I
224 1024 12
224 1024 18
224 1024 25
224 2048 25
224 1024 36
224 2048 36
224 1024 44
224 2048 44
I - Debugging integrated on chip.
PIC16(L)F15354/5 Data Sheet, 28-Pin
PIC16(L)F15325/45 Data Sheet, 14/20-Pin
PIC16(L)F15313/23 Data Sheet, 8/14-Pin
PIC16(L)F15324/44 Data Sheet, 14/20-Pin
PIC16(L)F15356/75/76/85/86 Data Sheet, 28/40/48-Pin
For other small form-factor package availability and marking information, please visit
www.microchip.com/pack-
aging
or contact your local sales office.
2016 Microchip Technology Inc.
Preliminary
DS40001853A-page 3
Debug
(1)
I/OPins
CWG
NCO
CLC
PIC16(L)F15354/55
TABLE 2:
Device
PIC16(L)F15313
PIC16(L)F15323
PIC16(L)F15324
PIC16(L)F15325
PIC16(L)F15344
PIC16(L)F15345
PIC16(L)F15354
PIC16(L)F15355
PIC16(L)F15356
PIC16(L)F15375
PIC16(L)F15376
PIC16(L)F15385
PIC16(L)F15386
PACKAGES
(S)PDIP SOIC SSOP TSSOP
X
X
X
X
X
X
X
X
X
X
X
—
—
X
X
X
X
X
X
X
X
X
—
—
—
—
—
—
—
—
X
X
X
X
X
—
—
—
—
—
X
X
X
—
—
—
—
—
—
—
—
—
(U)DFN QFN
(3x3) (4x4)
X
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
—
—
—
—
—
—
—
QFN UQFN
QFN UQFN UQFN
TQFP
(6x6) (4x4)
(8x8) (5x5) (6x6)
—
—
—
—
—
—
X
X
X
—
—
—
—
—
X
X
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
—
—
—
—
—
—
—
—
—
X
X
—
—
—
—
—
—
—
—
—
—
—
X
X
—
—
—
—
—
—
—
—
X
X
—
—
—
X
X
DS40001853A-page 4
Preliminary
2016 Microchip Technology Inc.
PIC16(L)F15354/55
PIN DIAGRAMS
28-pin PDIP, SOIC, SSOP
V
PP
/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
RC0
RC1
RC2
RC3
1
2
3
4
28
27
26
25
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
RC6
RC5
RC4
5
6
7
8
9
10
11
12
13
14
PIC16(L)F15354/55
24
23
22
21
20
19
18
17
16
15
Note 1:
2:
See
Table 2
for location of all peripheral functions.
All V
DD
and all V
SS
pins must be connected at the circuit board level.
28-pin QFN (6x6), UQFN (4x4), UQFN (6x6)
RA1
RA0
RE3/MCLR/V
PP
RB7
RB6
RB5
RB4
28
27
26
25
24
23
22
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
Note 1:
2:
3:
See
Table 2
for location of all peripheral functions.
All V
DD
and all V
SS
pins must be connected at the circuit board level. Allowing one or more V
SS
or V
DD
pins to
float may result in degraded electrical performance or non-functionality.
The bottom pad of the QFN/UQFN package should be connected to V
SS
at the circuit board level.
2016 Microchip Technology Inc.
RC0 8
RC1 9
RC2 10
RC3 11
RC4 12
RC5 13
RC6 14
1
2
3
4
5
6
7
PIC16(L)F15354/55
21
20
19
18
17
16
15
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
Preliminary
DS40001853A-page 5
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