INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT646
Octal bus transceiver/register;
3-state
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
FEATURES
•
Independent register for A and B buses
•
Multiplexed real-time and stored data
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT646 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT646 consist of bus transceiver circuits with
3-state outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from
the internal registers. Data on the “A” or “B” bus will be
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT646
clocked into the registers as the appropriate clock
(CP
AB
and CP
BA
) goes to a HIGH logic level. Output
enable (OE) and direction (DIR) inputs are provided to
control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source
inputs (S
AB
and S
BA
) can multiplex stored and real-time
(transparent mode) data. The direction (DIR) input
determines which bus will receive data when OE is active
(LOW). In the isolation mode (OE = HIGH), “A” data may
be stored in the “B” register and/or “B” data may be stored
in the “A” register.
When an output function is disabled, the input function is
still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.
The “646” is functionally identical to the “648”, but has
non-inverting data paths.
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay
input capacitance
power dissipation capacitance per channel
notes 1 and 2
A
n
, B
n
to B
n
, A
n
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
11
69
3.5
30
maximum clock frequency
HCT
13
85
3.5
33
ns
MHz
pF
pF
UNIT
September 1993
2
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
PIN DESCRIPTION
PIN NO.
1
2
3
4, 5, 6, 7, 8, 9, 10, 11
12
20, 19, 18, 17, 16, 15, 14, 13
21
22
23
24
SYMBOL
CP
AB
S
AB
DIR
A
0
to A
7
GND
B
0
to B
7
OE
S
BA
CP
BA
V
CC
NAME AND FUNCTION
74HC/HCT646
A to B clock input (LOW-to-HIGH, edge-triggered)
select A to B source input
direction control input
A data inputs/outputs
ground (0 V)
B data inputs/outputs
output enable input (active LOW)
select B to A source input
B to A clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
Octal bus transceiver/register; 3-state
74HC/HCT646
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
(1)
OE
H
H
L
L
L
L
Notes
1. H
L
X
↑
= HIGH voltage level
= LOW voltage level
= don’t care
= LOW-to-HIGH level transition
DIR
X
X
L
L
H
H
CP
AB
H or L
↑
X
X
X
H or L
CP
BA
H or L
↑
X
H or L
X
X
X
X
X
X
L
H
S
AB
X
X
L
H
X
X
S
BA
DATA I/O
(2)
FUNCTION
A
0
to A
7
input
output
input
B
0
to B
7
input
input
output
isolation
store A and B data
real-time B data to A bus
stored B data to A bus
real-time A data to B bus
stored A data to B bus
2. The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
September 1993
4
Analogue and Mixed Signal
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