P4C1024-20L1M datasheet, PDF - EEWORLD Datasheet

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P4C1024-20L1M: DescriptionStandard SRAM, 128KX8, 20ns, CMOS, 0.400 X 0.820 INCH, LCC-32; Categorystorage storage; File Size923KB，14 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C1024-20L1M Overview

Standard SRAM, 128KX8, 20ns, CMOS, 0.400 X 0.820 INCH, LCC-32

P4C1024-20L1M Parametric

Parameter Name	Attribute value
Maker	Pyramid Semiconductor Corporation
Parts packaging code	LCC
package instruction	SON,
Contacts	32
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	20 ns
JESD-30 code	R-XDSO-N32
length	21.082 mm
memory density	1048576 bit
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX8
Package body material	UNSPECIFIED
encapsulated code	SON
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Maximum seat height	2.54 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
width	10 mm

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P4C1024

HIGH SPEED 128K x 8

DUAL CHIP ENABLE

CMOS STATIC RAM

FEATURES

High Speed (Equal Access and Cycle Times)

— 15/20/25/35 ns (Commercial/Industrial)

— 20/25/35/45/55/70/85/100/120 ns (Military)

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using

and

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Fast t

Automatic Power Down

Packages

—32-Pin 300 mil DIP and SOJ

—32-Pin 400 mil SOJ

—32-Pin 600 mil Ceramic DIP

—32-Pin 400 mil Ceramic DIP

—32-Pin Solder Seal Flatpack

—32-Pin LCC (450 x 550 mil)

—32-Pin LCC (400 x 820 mil) [Two-Sided]

—32-Pin Ceramic SOJ

DESCRIPTION

The P4C1024 is a 1,048,576-bit high-speed CMOS

static RAM organized as 128Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times of 15 nanoseconds permit greatly en-

hanced system operating speeds. CMOS is utilized to

reduce power consumption to a low level. The P4C1024

is a member of a family of PACE RAM™ products offer-

ing fast access times.

The P4C1024 device provides asynchronous operations

with matching access and cycle times. Memory loca-

tions are specified on address pins A

to A

. Reading

is accomplished by device selection (CE

low and CE

high) and output enabling (OE) while write enable (WE)

remains HIGH. By presenting the address under these

conditions, the data in the addressed memory location

is presented on the data input/output pins. The input/

output pins stay in the HIGH Z state when either

is HIGH or

or CE

is LOW.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

DIP (P300, C10, C11),

SOJ (J300, J400, CJ1),

LCC (L1),

SOLDER SEAL

FLATPACK (FS-3) SIMILAR

LCC (L6)

Document #

SRAM124

REV C

Revised December 2011

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