SDRAM 64Mb H-die (x4, x8, x16)
CMOS SDRAM
64Mb H-die SDRAM Specification
Revision 1.8
August 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.8 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
Revision History
Revision 0.0 (May, 2003)
- Target spec release
Revision 0.1 (July, 2003)
- Preliminary spec release
Revision 0.2 (August, 2003)
- Modified IBIS characteristic.
Revision 1.0 (September, 2003)
- Finalized.
Revision 1.1 (September, 2003)
- Corrected IBIS Specification.
Revision 1.2 (October, 2003)
- Deleted speed 7C at x4/x8.
Revision 1.3 (October, 2003)
- Deleted AC parameter notes 5.
Revision 1.4 (November, 2003)
- Modified Pin Function description.
Revision 1.5 (February, 2004)
- Corrected typo.
Revision 1.6 (March, 2004)
- Modified Pin Description.
Revision 1.7 (May, 2004)
- Added Note 5. sentense of tRDL parameter.
CMOS SDRAM
Revision 1.8 (August, 2004)
- Modified CLK cycle time(tcc) parameter in AC Characteristics.
( If you want use of CL=2 not CL=3, the maximum operating frequency is 100MHz regardless of its speed bin.)
Rev. 1.8 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x
4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
K4S640432H-TC(L)75
K4S640832H-TC(L)75
K4S641632H-TC(L)60
K4S641632H-TC(L)70
K4S641632H-TC(L)75
4Mb x 16
Orgainization
16Mb x 4
8Mb x 8
Max Freq.
133MHz(CL=3)
133MHz(CL=3)
166MHz(CL=3)
143MHz(CL=3)
133MHz(CL=3)
LVTTL
54pin TSOP(II)
Interface
Package
Organization
16Mx4
8Mx8
4Mx16
Row Address
A0~A11
A0~A11
A0~A11
Column Address
A0-A9
A0-A8
A0-A7
Row & Column address configuration
Rev. 1.8 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
Package Physical Dimension
CMOS SDRAM
0~8°C
0.25
TYP
0.010
#54
#28
0.45~0.75
0.018~0.030
0.05
MIN
0.002
( 0.50 )
0.020
11.76±
0.20
0.463±
0.008
#1
22.62
MAX
0.891
22.22
0.875
0.10
MAX
0.004
(
0.71
)
0.028
±
0.10
±
0.004
#27
0.21
0.008
±
0.05
±
0.002
1.00
0.039
±
0.10
±
0.004
0.30
-0.05
0.012
+0.004
-0.002
+0.10
0.80
0.0315
54Pin TSOP(II) Package Dimension
10.16
0.400
0.125
+0.075
-0.035
0.005
+0.003
-0.001
1.20
MAX
0.047
Rev. 1.8 August 2004
SDRAM 64Mb H-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
4M x 4 / 2M x 8 / 1M x 16
Sense AMP
4M x 4 / 2M x 8 / 1M x 16
4M x 4 / 2M x 8 / 1M x 16
4M x 4 / 2M x 8 / 1M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
Programming Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
*
Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.8 August 2004
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