DATASHEET
KAD5512HP
High Performance 12-Bit, 250/210/170/125MSPS ADC
The KAD5512HP is the high performance member of the
KAD5512 family of 12-bit analog-to-digital converters. Designed
with Intersil’s proprietary FemtoCharge™ technology on a
standard CMOS process, the family supports sampling rates of
up to 250MSPS. The KAD5512HP is part of a pin-compatible
portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging
from 125MSPS to 500MSPS.
A Serial Peripheral Interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512HP is available in 72 and 48 Ld QFN
packages with an exposed paddle. Operating from a 1.8V
supply, performance is specified across the full industrial
temperature range (-40°C to +85°C).
FN6808
Rev 4.00
May 31, 2016
Features
• Pin-compatible with the KAD5512P Family, offering 2.2dB
higher SNR
• Programmable gain, offset and skew control
• 950MHz analog input bandwidth
• 60fs Clock jitter
• Over-range indicator
• Selectable clock divider: ÷1, ÷2 or ÷4
• Clock phase selection
• Nap and sleep modes
• Two’s complement, gray code or binary data format
• DDR LVDS-compatible or LVCMOS outputs
• Programmable built-in test patterns
• Single-supply 1.8V operation
• Pb-free (RoHS compliant)
Key Specifications
• SNR = 68.2dBFS for f
IN
= 105MHz (-1dBFS)
• SFDR = 81.1dBc for f
IN
= 105MHz (-1dBFS)
• Power Consumption
- 429/345mW at 250/125MSPS (SDR Mode)
- 390/309mW at 250/125MSPS (DDR Mode)
Applications
• Power Amplifier linearization
• Radar and satellite antenna array processing
• Broadband communications
• High-performance data acquisition
• Communications test equipment
• WiMAX and microwave receivers
CLKDIV
CLKP
CLKN
OVDD
AVDD
CLOCK
GENERATION
CLKOUTP
CLKOUTN
D[11:0]P
VINP
SHA
VINN
VCM
+
–
12-BIT
250 MSPS
ADC
DIGITAL
ERROR
CORRECTION
LVDS/CMOS
DRIVERS
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
1.25V
SPI
CONTROL
NAPSLP
FIGURE 1. BLOCK DIAGRAM
FN6808 Rev 4.00
May 31, 2016
OVSS
AVSS
CSB
SCLK
SDIO
SDO
Page 1 of 34
KAD5512HP
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Descriptions - 72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration - 72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Descriptions - 48 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Configuration - 48 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User-Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
18
18
19
20
20
20
20
20
20
21
22
23
24
24
24
25
26
27
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
72 Ld/48 Ld Package Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
30
30
30
30
30
30
30
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
L48.7x7E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
L72.10x10D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FN6808 Rev 4.00
May 31, 2016
Page 2 of 34
KAD5512HP
Ordering Information
PART NUMBER
(Note
3)
KAD5512HP-25Q72 (Note
1)
KAD5512HP-21Q72 (Note
1)
KAD5512HP-17Q72 (Note
1)
KAD5512HP-12Q72 (Note
1)
KAD5512HP-25Q48 (Note
2)
KAD5512HP-21Q48 (Note
2)
KAD5512HP-17Q48 (Note
2)
KAD5512HP-12Q48 (Note
2)
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu
plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for
KAD5512HP-12, KAD5512HP-17, KAD5512HP-21, KAD5512HP-25.
For more information on MSL, please see tech brief
TB363.
TABLE 1. PIN-COMPATIBLE FAMILY
MODEL
KAD5514P-25
KAD5514P-21
KAD5514P-17
KAD5514P-12
KAD5512P-50
KAD5512P-25, KAD5512HP-25
KAD5512P-21, KAD5512HP-21
KAD5512P-17, KAD5512HP-17
KAD5512P-12, KAD5512HP-12
KAD5510P-50
RESOLUTION
14
14
14
14
12
12
12
12
12
10
SPEED
(MSPS)
250
210
170
125
500
250
210
170
125
500
PART MARKING
KAD5512HP-25 Q72EP-I
KAD5512HP-21 Q72EP-I
KAD5512HP-17 Q72EP-I
KAD5512HP-12 Q72EP-I
KAD5512HP-25 Q48EP-I
KAD5512HP-21 Q48EP-I
KAD5512HP-17 Q48EP-I
KAD5512HP-12 Q48EP-I
SPEED
(MSPS)
250
210
170
125
250
210
170
125
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
(RoHS Compliant)
72 Ld QFN
72 Ld QFN
72 Ld QFN
72 Ld QFN
48 Ld QFN
48 Ld QFN
48 Ld QFN
48 Ld QFN
PKG. DWG. #
L72.10x10D
L72.10x10D
L72.10x10D
L72.10x10D
L48.7x7E
L48.7x7E
L48.7x7E
L48.7x7E
FN6808 Rev 4.00
May 31, 2016
Page 3 of 34
KAD5512HP
Absolute Maximum Ratings
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
48 Ld QFN (Note
4).
. . . . . . . . . . . . . . . . . . .
25
72 Ld QFN (Notes
4, 5)
. . . . . . . . . . . . . . . .
24
0.8
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
5. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
A
= -40°C to +85°C (typical specifications at +25°C), A
IN
= -1dBFS, f
SAMPLE
= maximum conversion rate (per speed grade).
KAD5512HP-25
(Note
6)
MIN
TYP
MAX
KAD5512HP-21
(Note
6)
MIN
TYP
MAX
KAD5512HP-17
(Note
6)
MIN
TYP
MAX
KAD5512HP-12
(Note
6)
MIN
TYP
MAX
UNIT
PARAMETER
DC SPECIFICATIONS
Analog Input
Full-Scale Analog
Input Range
Input Resistance
Input Capacitance
Full-Scale Range
Temperature Drift
Input Offset Voltage
Gain Error
Common-Mode
Output Voltage
Clock Inputs
Inputs
Common-Mode
Voltage
CLKP, CLKN Input
Swing
Power Requirements
1.8V Analog Supply
Voltage
1.8V Digital Supply
Voltage
1.8V Analog Supply
Current
1.8V Digital Supply
Current (SDR)
(Note
7)
SYMBOL
TEST
CONDITIONS
V
FS
R
IN
C
IN
A
VTC
V
OS
E
G
V
CM
Differential
Differential
Differential
Full Temperature
1.40
1.47
500
2.6
90
1.54
1.40
1.47
500
2.6
90
1.54
1.40
1.47
500
2.6
90
1.54
1.40
1.47
500
2.6
90
1.54
V
P-P
Ω
pF
ppm/
°C
-10
±2
±2
0.535
10
-10
±2
±2
0.535
10
-10
±2
±2
0.535
10
-10
±2
±2
0.535
10
mV
%
V
0.9
0.9
0.9
0.9
V
1.8
1.8
1.8
1.8
V
AVDD
OVDD
I
AVDD
I
OVDD
3mA LVDS
1.7
1.7
1.8
1.8
170
68
1.9
1.9
190
76
1.7
1.7
1.8
1.8
157
66
1.9
1.9
176
74
1.7
1.7
1.8
1.8
145
64
1.9
1.9
163
72
1.7
1.7
1.8
1.8
129
62
1.9
1.9
147
70
V
V
mA
mA
FN6808 Rev 4.00
May 31, 2016
Page 4 of 34
KAD5512HP
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
A
= -40°C to +85°C (typical specifications at +25°C), A
IN
= -1dBFS, f
SAMPLE
= maximum conversion rate (per speed grade). (Continued)
KAD5512HP-25
(Note
6)
MIN
TYP
46
MAX
KAD5512HP-21
(Note
6)
MIN
TYP
44
MAX
KAD5512HP-17
(Note
6)
MIN
TYP
43
MAX
KAD5512HP-12
(Note
6)
MIN
TYP
42
MAX
UNIT
mA
PARAMETER
1.8V Digital Supply
Current (DDR)
(Note
7)
Power Supply
Rejection Ratio
SYMBOL
I
OVDD
TEST
CONDITIONS
3mA LVDS
PSRR
30MHz, 200mV
P-P
signal on AVDD
-36
-36
-36
-36
dB
Total Power Dissipation
Normal Mode (SDR)
Normal Mode (DDR)
Nap Mode
Sleep Mode
Nap Mode Wake-up
Time (Note
8)
Sleep Mode Wake-up
Time (Note
8)
AC SPECIFICATIONS
Differential
Nonlinearity
Integral Nonlinearity
Minimum
Conversion Rate
(Note
9)
Maximum
Conversion Rate
Signal-to-Noise Ratio
DNL
INL
f
S
MIN
-0.75
-2.0
±0.2
±0.6
0.75
2.0
40
-0.75
-2.0
±0.2
±1.1
0.75
2.0
40
-0.75
-2.0
±0.2
±1.1
0.75
2.0
40
-0.75
-2.5
±0.2
±1.4
0.75
2.5
40
LSB
LSB
MSPS
P
D
P
D
P
D
P
D
CSB at logic high
Sample clock
running
Sample clock
running
3mA LVDS
3mA LVDS
429
390
148
2
1
1
170.2
6
463
402
363
142
2
1
1
164.2
6
433
378
339
136
2
1
1
158.2
6
406
345
309
129
2
1
1
150.2
6
376
mW
mW
mW
mW
µs
ms
f
S
MAX
SNR
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
250
68.3
65.9
68.2
67.8
66.8
64.4
62.4
68.2
65.6
68.0
67.5
66.0
59.1
48.6
11.0
10.6
11.0
10.9
10.7
9.5
7.8
210
68.8
66.4
68.7
68.3
67.3
64.9
62.9
68.7
66.1
68.7
68.0
66.4
59.1
48.2
11.1
10.7
11.1
11.0
10.7
9.5
7.7
170
69.1
67.1
68.9
68.6
67.8
65.7
63.8
69.0
66.6
68.7
68.2
66.7
60.0
49.2
11.2
10.8
11.1
11.0
10.8
9.7
7.9
125
69.3
67.1
69.1
68.7
67.7
65.2
63.1
69.2
66.6
68.9
68.4
66.8
59.8
50.5
11.2
10.8
11.1
11.1
10.8
9.6
8.1
MSPS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Bits
Signal-to-Noise and
Distortion
SINAD
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
Effective Number of
Bits
ENOB
f
IN
= 10MHz
f
IN
= 105MHz
f
IN
= 190MHz
f
IN
= 364MHz
f
IN
= 695MHz
f
IN
= 995MHz
FN6808 Rev 4.00
May 31, 2016
Page 5 of 34
MCU
京公网安备 11010802033920号
EEWORLD
