MT9VDDF3272IY-265XX datasheet, PDF

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MT9VDDF3272IY-265XX: DescriptionDDR DRAM Module, 32MX72, 0.75ns, CMOS, LEAD FREE, DIMM-184; Categorystorage storage; File Size750KB，34 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT9VDDF3272IY-265XX Overview

DDR DRAM Module, 32MX72, 0.75ns, CMOS, LEAD FREE, DIMM-184

MT9VDDF3272IY-265XX Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	184
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.75 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N184
JESD-609 code	e4
memory density	2415919104 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	184
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	32MX72
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Gold (Au)
Terminal form	NO LEAD
Terminal location	DUAL
Maximum time at peak reflow temperature	30

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256MB, 512MB (x72, ECC, SR)

184-PIN DDR SDRAM RDIMM

DDR SDRAM

REGISTERED DIMM

Features

• 184-pin, dual, in-line memory module (DIMM)

• Fast data transfer rates: PC1600, PC2100, or PC2700

• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR

SDRAM components

• Registered Inputs with one-clock delay

• Phase-lock loop (PLL) clock driver to reduce loading

• Supports ECC error detection and correction

• 256MB (32 Meg x 72); and 512MB (64 Meg x 72)

• V

= V

DDQ

= +2.5V

• V

DDSPD

= +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/received

with data—i.e., source-synchronous data capture

• Differential clock inputs CK and CK#

• Four internal device banks for concurrent operation

• Programmable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 7.8125µs maximum average periodic refresh

interval

• Serial Presence-Detect (SPD) with EEPROM

• Programmable READ CAS latency

• Gold edge contacts

OPTIONS

MARKING

MT9VDDF3272 – 256MB

MT9VDDF6472 – 512MB

For the latest data sheet, please refer to the Micron



Web

site:

www.micron.com/products/modules

Figure 1: 184-Pin DIMM (MO-206)

Low-Profile 1.125in. (28.58mm) 256MB

Low-Profile 1.125in. (28.58mm) 512MB

Very Low-Profile 0.72in. (18.29mm)

OPTIONS

MARKING

• Operating Temperature Range

Commercial (0°C

≤

+70°C)

Industrial (-40°C

≤

+85°C)

• Package

184-pin DIMM (standard)

184-pin DIMM (lead-free)

• Memory Clock, Speed, CAS Latency

6ns (167 MHz), 333 MT/s, CL = 2.5

7.5ns (133 MHz), 266 MT/s, CL = 2

7.5ns (133 MHz), 266 MT/s, CL = 2.5

10ns (100 MHz), 200 MT/s, CL = 2

• PCB

Low-Profile 1.125in. (28.58mm)

Very Low-Profile 0.72in. (18.29mm)

NOTE:

-335

-262

-26A

-265

-202

none

1. Contact Micron for product availability.

2. CL = CAS (READ) Latency; Registered mode will

add one clock cycle to CL.

Table 1:

Address Table

256MB

512MB

8K (A0–A12)

4 (BA0, BA1)

512Mb (64 Meg x 8)

2K (A0–A9, A11)

1 (S0#)

8K (A0–A12)

4 (BA0, BA1)

256Mb (32 Meg x 8)

1K (A0–A9)

1 (S0#)

Refresh Count

Row Addressing

Device Bank Addressing

Device Configuration

Column Addressing

Module Rank Addressing

pdf: 09005aef80e119b2, source: 09005aef807d56a1

DDF9C32_64x72G.fm - Rev. B 9/04 EN

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

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