MT9LSDT1672Y-13EXX datasheet, PDF

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MT9LSDT1672Y-13EXX: DescriptionSynchronous DRAM Module, 16MX72, 5.4ns, CMOS, LEAD FREE, DIMM-168; Categorystorage storage; File Size676KB，14 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT9LSDT1672Y-13EXX Overview

Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, LEAD FREE, DIMM-168

MT9LSDT1672Y-13EXX Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	168
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N168
JESD-609 code	e4
memory density	1207959552 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	168
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	55 °C
Minimum operating temperature
organize	16MX72
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Gold (Au)
Terminal form	NO LEAD
Terminal location	DUAL
Maximum time at peak reflow temperature	30

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128MB, 256MB (x72, ECC, SR): 168-Pin SDRAM RDIMM

Features

SDRAM RDIMM

MT9LSDT1672 – 128MB

MT9LSDT3272 – 256MB

For component data sheets, refer to Micron’s Web site:

www.micron.com

Features

• 168-pin, PC133-compliant registered dual in-line

memory module (RDIMM)

• Phase-lock loop (PLL) clock driver to reduce loading

• Uses 133 MHz SDRAM components

• Supports ECC error detection and correction

• 128MB (16 Meg x 72) and 256MB (32 Meg x 72)

• V

= +3.3V

• Fully synchronous; all signals are registered on the

positive edge of the PLL clock

• Internal pipelined operation; column address can be

changed every clock cycle

• Internal SDRAM banks for hiding row access/

precharge

• Programmable burst lengths (BL): 1, 2, 4, 8, or full

page

• Single rank

• Auto precharge option

• Auto and self refresh modes: 15.625µs (128MB) or

7.81µs (256MB) maximum periodic refresh interval

• LVTTL-compatible inputs and outputs

• Serial presence-detect (SPD) with EEPROM

• Gold edge contacts

168-Pin RDIMM (MO-161 R/C A)

Figure 1:

Standard Layout

PCB height: 38.1mm (1.5in)

Figure 2:

Low Profile Layout

PCB height: 28.58mm (1.125in)

Options

Marking

• Package

–

168-pin DIMM

–

168-pin DIMM (Pb-free)

• Frequency/CAS latency

–

133 MHz/CL = 2

-13E

–

133 MHz/CL = 3

-133

Notes: 1. CL = CAS (READ) latency; registered mode

will add one clock cycle to CL.

Table 1:

Speed

Grade

-13E

-133

Key Timing Parameters

Data Rate (MT/s)

Industry

Nomenclature

PC133

CL = 2

133

–

CL = 3

–

133

RCD

(ns)

PDF: 09005aef80a2e32f/Source: 09005aef80a2e30d

SD9C16_32x72.fm - Rev. D 1/08 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

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