HEF4520B
Dual binary counter
Rev. 6 — 18 November 2011
Product data sheet
1. General description
The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an
active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs
from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous
master reset input (nMR).
The counter advances on either the LOW-to-HIGH transition of the nCP0 input if nCP1 is
HIGH or the HIGH-to-LOW transition of the nCP1 input if nCP0 is LOW. Either nCP0 or
nCP1 may be used as the clock input to the counter while the other clock input may be
used as a clock enable input. Schmitt trigger action makes the clock input highly tolerant
of slower clock rise and fall times. A HIGH on nMR resets the counter (nQ0 to
nQ3 = LOW) independent of nCP0 and nCP1.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +85
C.
Type number
HEF4520BP
HEF4520BT
Package
Name
DIP16
SO16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1
NXP Semiconductors
HEF4520B
Dual binary counter
4. Functional diagram
1Q0 3
1 1CP0
1Q1 4
2 1CP1
1Q2 5
1Q3 6
7 1MR
2Q0 11
9 2CP0
2Q1 12
10 2CP1
2Q2 13
2Q3 14
15 2MR
001aae698
Fig 1.
Functional diagram
1
nCP0
nCP1
nMR
1
nQ0
nQ1
nQ2
nQ
3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
001aae707
Fig 2.
Timing diagram
nQ0
nQ1
nQ2
nQ3
Q
nCP1
FF 1
T
CD Q
T
FF 2
Q
FF 3
T
CD Q
Q
FF 4
T
CD Q
Q
nCP0
CD Q
nMR
001aae705
Fig 3.
Logic diagram for one counter
HEF4520B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 18 November 2011
2 of 14
NXP Semiconductors
HEF4520B
Dual binary counter
5. Pinning information
5.1 Pinning
HEF4520B
1CP0
1CP1
1Q0
1Q1
1Q2
1Q3
1MR
V
SS
1
2
3
4
5
6
7
8
001aae704
16 V
DD
15 2MR
14 2Q3
13 2Q2
12 2Q1
11 2Q0
10 2CP1
9
2CP0
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
1CP0, 2CP0
1CP1, 2CP1
1Q0 to 1Q3
1MR, 2MR
V
SS
2Q0 to 2Q3
V
DD
Pin description
Pin
1, 9
2, 10
3, 4, 5, 6
7, 15
8
11, 12, 13, 14
16
Description
clock input (LOW-to-HIGH triggered)
clock input (HIGH-to-LOW triggered)
output
master reset input
ground supply voltage
output
supply voltage
6. Functional description
Table 3.
nCP0
L
X
H
X
[1]
Function table
[1]
nCP1
H
X
L
X
nMR
L
L
L
L
L
L
H
Mode
counter advances
counter advances
no change
no change
no change
no change
nQ0 to nQ3 = LOW
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition;
= negative-going transition.
HEF4520B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 18 November 2011
3 of 14
NXP Semiconductors
HEF4520B
Dual binary counter
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
P
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+85
750
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
mW
per output
DIP16 package
SO16 package
[1]
[2]
65
40
-
-
-
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
8. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Typ
-
-
-
-
-
-
Max
15
V
DD
+85
3.75
0.5
0.08
Unit
V
V
C
s/V
s/V
s/V
HEF4520B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 18 November 2011
4 of 14
NXP Semiconductors
HEF4520B
Dual binary counter
9. Static characteristics
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level input voltage
I
O
< 1
A
5V
10 V
15 V
V
OH
HIGH-level output voltage
I
O
< 1
A;
V
I
= V
SS
or V
DD
I
O
< 1
A;
V
I
= V
SS
or V
DD
5V
10 V
15 V
V
OL
LOW-level output voltage
5V
10 V
15 V
I
OH
HIGH-level output current V
O
= 2.5 V
V
O
= 4.6 V
V
O
= 9.5 V
V
O
= 13.5 V
I
OL
LOW-level output current
V
O
= 0.4 V
V
O
= 0.5 V
V
O
= 1.5 V
I
I
I
DD
input leakage current
supply current
V
DD
= 15 V
I
O
= 0 A;
V
I
= V
SS
or V
DD
5V
5V
10 V
15 V
5V
10 V
15 V
15 V
5V
10 V
15 V
C
I
input capacitance
-
T
amb
=
40 C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.52
1.3
3.6
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.7
0.52
1.3
3.6
-
-
-
0.3
20
40
80
-
T
amb
= 25
C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.44
1.1
3.0
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.4
0.44
1.1
3.0
-
-
-
0.3
20
40
80
7.5
T
amb
= 85
C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.1
0.9
2.4
-
-
-
1.0
150
300
600
-
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
A
A
A
A
pF
Unit
0.36
mA
10. Dynamic characteristics
Table 7.
Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C; for test circuit see
Figure 6;
unless otherwise specified.
Symbol
t
PHL
Parameter
HIGH to LOW
propagation delay
Conditions
nCP0, nCP1
nQn;
see
Figure 5
V
DD
5V
10 V
15 V
nMR
nQn;
see
Figure 5
5V
10 V
15 V
[1]
Extrapolation formula
83 ns + (0.55 ns/pF)C
L
39 ns + (0.23 ns/pF)C
L
32 ns + (0.16 ns/pF)C
L
48 ns + (0.55 ns/pF)C
L
24 ns + (0.23 ns/pF)C
L
17 ns + (0.16 ns/pF)C
L
Min
-
-
-
-
-
-
Typ
110
50
40
75
35
25
Max
220
100
80
150
70
50
Unit
ns
ns
ns
ns
ns
ns
HEF4520B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 18 November 2011
5 of 14
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