FEDL610Q101-03
Issue Date: Aug. 4, 2015
ML610Q101/ML610Q102
8-bit Microcontroller
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as timers,
PWM, UART, voltage level supervisor (VLS) function, and 10-bit successive approximation type A/D converter,
are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipe line
architecture parallel processing.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
•
CPU
−
8-bit RISC CPU (CPU name: nX-U8/100)
−
Instruction system: 16-bit instructions
−
Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit
logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
−
On-Chip debug function
−
Minimum instruction execution time
30.5µs (@32.768kHz system clock)
0.122µs (@8.192MHz system clock)
•
Internal memory
−
ML610Q101 : Internal 4Kbyte Flash ROM (2K×16 bits) (including unusable 32 byte test data area)
−
ML610Q102 : Internal 6Kbyte Flash ROM (3K×16 bits) (including unusable 32 byte test data area)
−
Internal 256byte data RAM (256×8 bits)
•
Interrupt controller
−
1 non-maskable interrupt source (Internal source: 1)
−
21 maskable interrupt sources (Internal sources: 16, External sources: 5)
•
Time base counter (TBC)
−
Low-speed time base counter
×1
channel
−
High-speed time base counter
×1
channel
•
Watchdog timer (WDT)
−
Non-maskable interrupt and reset
−
Free running
−
Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
•
Timer
−
8 bits
×
6 channels (16-bit configuration available)
−
Support Continuos timer mode/one shot timer mode
−
Timer start/stop function by software or external trigger input
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FEDL610Q101-03
ML610Q101/ML610Q102
•
PWM
−
Resolution 16 bits
×
1 channel
−
Support Continuos timer mode/one shot timer mode
−
PWM start/stop function by software or external trigger input
•
UART
−
Half-duplex
−
TXD/RXD
×
1 channels
−
Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
−
Positive logic/negative logic selectable
−
Built-in baud rate generator
•
Successive approximation type A/D converter (SA-ADC)
−
10-bit A/D converter
−
Input
×
6 channels
•
Analog Comparator
−
Operating voltage: V
DD
= 2.7V to 5.5V
−
Input voltage by common mode: V
DD
= 0.1V to V
DD
- 1.5V
−
Hysteresis (Comparator0 only): 20mV(Typ.)
−
Allows selection of interrupt disabled mode,falling-edge interrupt mode,rising-edge interrupt mode,
or both-edge interrupt mode.
•
General-purpose ports (GPIO)
−
Input/output port
×
11 channels (including secondary functions)
•
Reset
−
Reset by the RESET_N pin
−
Reset by power-on detection
−
Reset by the watchdog timer (WDT) overflow
−
Reset by voltage level supervisor(VLS)
•
Voltage level supervisor(VLS)
−
Judgment accuracy:
±3.0%
(Typ.)
−
It can be used for low level detection reset.
•
Clock
−
Low-speed clock:
Built-in RC oscillation (32.768 kHz)
−
High-speed clock:
Built-in PLL oscillation (16.384 MHz), external clock
The clock of the CPU is 8.192MHz(Max)
−
Selection of high-speed clock mode by software:
Built-in PLL oscillation, external clock
•
Power management
−
HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
−
STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral
circuits are stopped.)
−
Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
−
Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused
peripherals.
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FEDL610Q101-03
ML610Q101/ML610Q102
•
Shipment
−
16-pin plastic SSOP
ML610Q101-xxxMB (Blank product: ML610Q101-NNNMB)
ML610Q102-xxxMB (Blank product: ML610Q102-NNNMB)
−
16-pin plastic WQFN
ML610Q101-xxxGD (Blank product: ML610Q101-NNNGD)
ML610Q102-xxxGD (Blank product: ML610Q102-NNNGD)
•
Guaranteed operating range
−
Operating temperature:
−40°C
to 85°C
−
Operating voltage: V
DD
= 2.7V to 5.5V
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FEDL610Q101-03
ML610Q101/ML610Q102
BLOCK DIAGRAM
ML610Q101 Block Diagram
Figure 1 show the block diagram of the ML610Q101.
"*" indicates secondary function, tertiary function or quaternary function of each port.
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ELR1½3
LR
EA
ALU
Instruction
Decoder
SP
Instruction
Register
Data-bus
BUS
Controller
ECSR1½3
DSR/CSR
PC
Program
Memory
(Flash)
4kbyte
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST
RESET &
TEST
INT
1
UART
RXD0
TXD0*
RAM
256byte
Interrupt
Controller
INT
1
OSC
Power
INT
1
AIN0*
to
AIN5*
10bit-ADC
INT
6
INT
2
CMP0P*
CMP0M*
1
CMP0POUT*
CMP0NOUT*
CMP1P*
CMP1OUT*
Analog
Comparator
×2
INT
4
WDT
INT
1
PWM
PWMC*
TBC
INT
5
PA0 to PA2
GPIO
PB0 to PB7
8bit Timer
×6
INT
1
VLS
Figure 1 ML610Q101 Block Diagram
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FEDL610Q101-03
ML610Q101/ML610Q102
ML610Q102 Block Diagram
Figure 2 show the block diagram of the ML610Q102.
"*" indicates secondary function, tertiary function or quaternary function of each port.
CPU (nX-U8/100)
EPSW1½3
PSW
Timing
Controller
GREG
0½15
ELR1½3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
BUS
Controller
Program
Memory
(Flash)
6kbyte
ECSR1½3
DSR/CSR
PC
On-Chip
ICE
V
DD
V
SS
RESET_N
TEST
Data-bus
INT
1
UART
RXD0
TXD0*
RESET &
TEST
RAM
256byte
OSC
INT
1
Power
INT
1
AIN0*
to
AIN5*
10bit-ADC
INT
6
INT
2
CMP0P*
CMP0M*
CMP0OUT*
CMP0POUT*
CMP0NOUT*
CMP1P*
CMP1OUT*
Analog
Comparator
×2
INT
4
Interrupt
Controller
WDT
INT
1
PWM
PWMC*
TBC
INT
5
GPIO
PA0 to PA2
PB0 to PB7
8bit Timer
×6
INT
1
VLS
Figure 2 ML610Q102 Block Diagram
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