UT54ACTS4002UVXR datasheet, PDF

UT54ACTS4002UVXR: DescriptionACT SERIES, DUAL 4-INPUT NOR GATE, CDFP14, FP-14; Categorylogic logic; File Size75KB，3 Pages; ManufacturerCobham Semiconductor Solutions

Download Datasheet Parametric View All

UT54ACTS4002UVXR Overview

ACT SERIES, DUAL 4-INPUT NOR GATE, CDFP14, FP-14

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Cobham Semiconductor Solutions
Parts packaging code	DFP
package instruction	DFP,
Contacts	14
Reach Compliance Code	unknown
series	ACT
JESD-30 code	R-CDFP-F14
JESD-609 code	e0
length	9.525 mm
Logic integrated circuit type	NOR GATE
Number of functions	2
Number of entries	4
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
propagation delay (tpd)	22 ns
Certification status	Not Qualified
Maximum seat height	2.921 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	6.2865 mm

How to implement “disconnection detection” of CAN bus?: I am currently working on a vehicle controller, and the software requirement requires a "CAN bus disconnection detection" alarm function, using MPC5604B. Does anyone know how to add it to the program?...; 小天1818 Automotive Electronics

Verilog and VHDL mixed programming: ISE, QII All currently popular compilers support mixed programming. The mixed programming method is very simple. If VHDL calls a module written in VERILOG language, we declare the module in VHDL langu...; eeleader FPGA/CPLD

[Goodbye 2021, Hello 2022] Repairing the plank road in the open, crossing the Chen Cang in secret: 2021 is almost over. Today is January 20, the Great Cold in the lunar calendar. I heard a piece of news that if Qing Dynasty China had defeated the West, the world would basically use the lunar calend...; ddllxxrr Talking

4-bit flashing light based on FPGA-simple design method: 4 flashing lights 1. Project Background The theory of LED lights and the schematic diagram of the teaching board have been described in detail in Case 1 : Flashing Light, so I will not repeat them her...; mdy-吴伟杰 FPGA/CPLD

[Beginner] What are prj and dtp files?: What can I use to open prj and dtp files? What can I use to compile s03?...; jyhsaka159 Embedded System

Naming rules for microcontrollers: I have studied microcontrollers for a long time, but I still don't quite understand the naming rules of microcontrollers, such as C51, C52, AT89C51, AT89S51, AT89S52, STC89S51, STC89S52. Which expert ...; komaoscar MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components