VSC8117QP datasheet, PDF - EEWORLD Datasheet

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VSC8117QP: DescriptionATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery; CategoryWireless rf/communication Telecom circuit; File Size228KB，22 Pages; ManufacturerVitesse Semiconductor Corporation; Websitehttp://www.vitesse.com/

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VSC8117QP Overview

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

VSC8117QP Parametric

Parameter Name	Attribute value
Maker	Vitesse Semiconductor Corporation
Objectid	1514802242
Parts packaging code	QFP
package instruction	FQFP,
Contacts	64
Reach Compliance Code	unknow
compound_id	6916581
app	ATM;SDH;SONET
JESD-30 code	S-PQFP-G64
length	10 mm
Number of functions	1
Number of terminals	64
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Certification status	Not Qualified
Maximum seat height	2.45 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	ATM/SONET/SDH TRANSCEIVER
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	10 mm

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8117

Features

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

•

Operates at Either STS-3/STM-1 (155.52Mb/s)

or STS-12/STM-4 (622.08Mb/s) Data Rates

• Compatible with Industry ATM UNI Devices

• On Chip Clock Generation of the

155.52MHz

622.08MHz High Speed Clock (Mux)

• On Chip Clock Recovery of the

155.52MHz or

622.08MHz High Speed Clock (Demux)

• 8 Bit Parallel TTL Interface

• SONET/SDH Frame Recovery

• Loss of Signal (LOS) Input & LOS Detection

• +3.3V/5V programmable PECL Serial Interface

• Provides Equipment, Facilities and Split Loop-

back Modes as well as Loop Timing Mode

• Provides TTL and PECL reference clock inputs

• Meets Bellcore, ITU and ANSI Specifications for

Jitter Performance

• Low Power - 1.0 Watts Typical

• 64 PQFP Package

General Description

The VSC8117 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication

Unit (PLL) for the high speed clock as well as a clock and data recovery unit (CRU) with 8 bit serial-to-parallel

and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direction (Mux).

The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer contains

SONET/SDH frame detection and recovery. The device provides facility loopback, equipment loopback, and

loop timing modes. The part is packaged in a 64-pin PQFP with integrated heat spreader for optimum thermal

performance and reduced cost. The VSC8117 provides an integrated solution for ATM physical layers and

SONET/SDH systems applications.

Functional Description

The VSC8117 is designed to provide a SONET/SDH compliant interface between the high speed optical

networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8117

converts 8 bit parallel data at 77.76Mb/s or 19.44Mb/s to a serial bit stream at 622.08Mb/s or 155.52Mb/s

respectively. The device also provides a Facility Loopback function which loops the received high speed data

and clock (optionally recovered on-chip) directly to the high speed transmit outputs. A Clock Multiplier Unit

(CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream

from input reference frequencies of 19.44 or 77.76 MHz. The CMU can be bypassed with the recovered clock in

loop timing mode thus synchronizing the entire part to a single clock. The block diagram on page 2 shows the

major functional blocks associated with the VSC8117.

The receive section provides the serial-to-parallel conversion, converting the 155.52Mb/s or 622.08Mb/s bit

stream to an 8 bit parallel output at 19.44Mb/s or 77.76Mb/s respectively. A Clock Recovery Unit (CRU) is inte-

grated into the receive circuit to recover the high speed clock from the received serial data stream. The receive

section provides an Equipment Loopback function which will loop the low speed transmit data and clock back

through the receive section to the 8 bit parallel data bus and clock outputs. The VSC8117 also provides the

option of selecting between either its internal CRU’s recovered clock and data signals or optics containing a

G52221-0, Rev. 4.1

1/8/00

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8117

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Transmit Section

Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKOUT.

TXLSCKOUT also latches TXIN[7:0] into the part as shown in Figure 1. The data is then serialized (MSB lead-

ing) and presented at the TXDATAOUT+/- pins. The serial output stream is synchronized to the CMU generated

clock which is a phase locked and frequency scaled version of the input reference clock. External control inputs

CMUFREQSEL and STS-12 select the multiply ratio of the CMU for either STS-3 (155MbS) or STS-12

(622Mb/s) transmission (see Table 10). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be

used to synchronize the transmit interface of the UNI device to the transmit input registers on the VSC8117.

Figure 1: Data and Clock Transmit Block Diagram

VSC8117

PM5355

TXDATAOUT+

TXDATAOUT-

Q D

TXIN[7:0]

Q D

TXLSCKIN

REFCLK

CMU

Divide-by-8

TXLSCKOUT

Receive Section

High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN

inputs. The CRU recovers the high speed clock from the serial data input. The serial data is converted to byte-

wide parallel data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock

(RXLSCKOUT) should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the

UNI device. The on-chip CRU is by-passed by setting the DSBLCRU input high. In this mode, the serial input

data and corresponding clock are received by the RXDATAIN and RXCLKIN inputs respectively. RXDATAIN

is clocked in on the rising edge of RXCLKIN+. See Figure 2.

The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH

frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the

byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock

cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8117 will con-

tinually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been

detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has

been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When

a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the

byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends a FP pulse only if OOF is high.

G52221-0, Rev. 4.1

1/8/00

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 3

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

Data Sheet

VSC8117

Loss of Signal

The VSC8117 features Loss of Signal (LOS) detection. Loss of Signal is declared if the incoming serial

data stream has no transition continuously for more than 128 bits. During an LOS condition, the VSC8117

forces the receive data low which is an indication for any downstream equipment that an optical interface failure

has occurred. The receive section continues to be clocked by the CRU as it is now locked to the CRUREFCLK

unless DSBLCRU is active or CRUREFSEL is inactive in which case it will be clocked by the CMU. This LOS

condition will be removed when the part detects more than 16 transitions in a 128 bit time window. This LOS

detection feature can be disabled by applying a high level to the LOSDETEN_ input. The VSC8117 also has a

PECL input LOSPECL to force the part into a Loss of Signal state. Most optics have a PECL output usually

called “SD” or “FLAG” indicating a lack of or presence of optical power. Depending on the optics manufacturer

this signal is either active high or active low. The LOSPECL input on the VSC8117 is active low.

Figure 2: Data and Clock Receive Block Diagram

VSC8117

LOSPECL

LOSDETEN_

DSBLCRU

RXDATAIN+/-

CRU

RXCLKIN+/-

CMU

Divide-by-8

RXLSCKOUT

D Q

RXOUT[7:0]

PM5355

D Q

Facility Loopback

The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set

high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented

to the high speed transmit output (TXDATAOUT). See Figure 3. In Facility Loopback mode the high speed

receive data (RXDATAIN) is also converted to parallel data and presented to the low speed receive data output

pins (RXOUT[7:0]). The receive clock (RXCLKIN) or the recovered clock is also divided down and presented

to the low speed clock output (RXLSCKOUT).

Page 4

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52221-0, Rev 4.1

1/8/00

VSC8117QP Related Products

	VSC8117QP	VSC8117QP2	VSC8117QP1	VSC8117
Description	ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery	ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery	ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery	ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
Maker	Vitesse Semiconductor Corporation	Vitesse Semiconductor Corporation	Vitesse Semiconductor Corporation	-
Parts packaging code	QFP	QFP	QFP	-
package instruction	FQFP,	FQFP,	FQFP,	-
Contacts	64	64	64	-
Reach Compliance Code	unknow	unknow	unknow	-
app	ATM;SDH;SONET	ATM;SDH;SONET	ATM;SDH;SONET	-
JESD-30 code	S-PQFP-G64	S-PQFP-G64	S-PQFP-G64	-
length	10 mm	10 mm	10 mm	-
Number of functions	1	1	1	-
Number of terminals	64	64	64	-
Maximum operating temperature	70 °C	85 °C	85 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	FQFP	FQFP	FQFP	-
Package shape	SQUARE	SQUARE	SQUARE	-
Package form	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
Maximum seat height	2.45 mm	2.45 mm	2.45 mm	-
Nominal supply voltage	3.3 V	3.3 V	3.3 V	-
surface mount	YES	YES	YES	-
Telecom integrated circuit types	ATM/SONET/SDH TRANSCEIVER	ATM/SONET/SDH TRANSCEIVER	ATM/SONET/SDH TRANSCEIVER	-
Temperature level	COMMERCIAL	INDUSTRIAL	OTHER	-
Terminal form	GULL WING	GULL WING	GULL WING	-
Terminal pitch	0.5 mm	0.5 mm	0.5 mm	-
Terminal location	QUAD	QUAD	QUAD	-
width	10 mm	10 mm	10 mm	-

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