on the CS input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
2. Tested on a sample basis.
3. 20 pF on CS, 70 pF all others.
Document #: 38-05261 Rev. *A
Page 3 of 9
CYM1841B
Switching Characteristics
Over the Operating Range
[4]
1841B-15
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
CS HIGH to High
[5]
1841B-20
Min.
20
Max.
1841B-25
Min.
25
Max.
Unit
ns
25
3
25
8
0
8
4
8
18
25
20
20
0
2
15
8
2
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
15
Max.
15
3
15
7
0
7
3
7
15
15
10
10
0
2
12
7
1
0
0
[4]
20
3
20
8
0
8
4
8
18
20
15
18
0
2
15
8
2
0
Z
[5, 6]
CS HIGH to Power-Down
Write Cycle Time
CS LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[6]
Write Cycle
[7]
6
0
8
0
Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
PD
Write Cycle
[7]
t
WC
Write Cycle Time
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE LOW to High Z
CS LOW to Low Z
[5]
CS HIGH to High Z
[5, 6]
CS HIGH to Power-Down
Description
1841B-35
Min.
35
35
3
35
25
0
15
10
20
35
35
45
10
0
3
Max.
1841B-45
Min.
45
45
45
30
15
20
45
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. At any given temperature and voltage condition, t
HZCS
is less than t
LZCS
for any given device. These parameters are guaranteed by design and not 100% tested.
6. t
HZCS
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05261 Rev. *A
Page 4 of 9
CYM1841B
Switching Characteristics
Over the Operating Range (continued)
[4]
1841B-35
Parameter
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Description
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[6]
Min.
30
30
2
2
30
20
2
0
0
15
Max.
40
40
2
2
35
25
2
0
0
15
1841B-45
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Waveforms
Read Cycle No. 1
[8, 9]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2
[8, 10]
CS
t
ACS
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
DATA OUT
t
LZCS
Notes:
8. WE is HIGH for read cycle.
9. Device is continuously selected, CS = V
IL
and OE= V
IL
.
10. Address valid prior to or coincident with CS transition LOW.
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